Which is DFT/BE Friendly Design for Independently Gated Divided Clocks

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Which is DFT/BE Friendly Design for Independently Gated Divided Clocks

A simple clock divider circuit is as below. Multiple flip-flops work together as a counter. Based on the counter out, we can generate divided clock. For example, when counter reaches 23, counter goes back to 0 and also we assert clk_div_out=1 otherwise clk_div_out=0. Then clk_div_out is clk_in/24.

Experienced designers can tell this circuit has an issue. Clk_div_out is combinational logic output and therefore is glitchy. It can not be used as clock directly.

Here is a way to use a FF to absorb glitch and new clk_div_out can be used as clock. Let’s call this FF as deglitch FF.

This post is to discuss the use case that we need to generate multiple divided down clocks of the same clock rate but each of them can be independently gated off. Below is the one way to achieve it. Two ICGs, clock gating cells, are placed after the deglitch FF.

Next we will show two other ways to do it. Although “function” wise they are the same we will discuss their cons and pros from DFT and backend point of view.

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Highlights: 459 words, 3 images
ASIC and Process Engineer
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1 Comment
  1. mazhar 2 months ago

    Thank you for sharing.


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