Lack of signal force support in VHDL is really a headache to verification engineers. Unfortunately I ran into this issue recently. A signal in VHDL has to be forced in test bench or I have to hack VHDL which is obviously not desired. Amid quite a bit…[Read more]
Get timing report from timing team. Surprise to see DC uses high delay cells which make the path failing the constraint by quite a bit. DC can easily use low delay cells to fix it. STA tool can fix it anyway. What really concerns me here is if DC takes…[Read more]
#dft difference of #Synchronous #reset and async reset
Sync abd async reset have their pros and cons. Rtl point of view, one signal can be connected to both async reset and sync reset. This is not true for dft. You will see async reset has one extra dft mux on the sync reset to add in dft…[Read more]
Check your clock constraints if so. Most cases it is not rtl issue. FFs are connected to a clock. But this clock is not defined in clock constraints. Synthesis and STA treat it as no clock since no clock information is available.
The idea is to send data from pc to fpga and then from fpga to spi flash. Pc to fpga communication can be done with uart. Fpga then implements an spi master module which converts uart data to spi data sent to flash from spi master module.
LWA (LTE/WLAN Aggregation) is a tight integration at radio level which allows for real-time channel and load aware radio resource management across #WLAN and #LTE to provide significant user perceived throughput (UPT) improvement. When enabling…[Read more]
#qualcomm ceo and others get low reelection vote and plan cost cut
Mollenkopf told investors following the company’s rejection of Broadcom’s bid that he could achieve earnings per share of $6.75 to $7.50 in fiscal 2019, through a number of measures, including a $1-billion cost red…[Read more]
Modelsim and vcs support using -y to specify source file folders. You can use -v to list all the verilog files you want to compile. But here is an issue. If some of your tests dont need some files, you may want to remove these files from file list otherwise…[Read more]
Another round of layoff just anounced. Surprise to most of us since product sells well. Senior and higher ranking guys are cut off more this time. Trim cost down and make room for youngers.
Now everyone is careful about their positions. Unwilling to share to make it harder to replace them.
Built from ARM’s Fast Model toolkit, ARM provides a number of ready-to-use simulation models of platforms containing ARM processors, referred to asFixed Virtual Platforms. This OpenEmbedded Engineering Build is designed to work with a number of those FVPs which contain A…[Read more]
A new Compute Through Power Loss (CPTL) tool suite and library developed at Texas Instruments’ Kilby Labs enables the use of checkpointing on limited resource 16-bit MCUs. When an MCU’s ope…[Read more]
Successfully used vivado HLS to synthesize cpp project into hw ip and havve it running on xilinx fpga. Note i said hw ip instead of rtl because generated rtl calls other xilinx cores which may further use other ips. There is NO file list to locate all the rtl…[Read more]
Read some ref. HLS generated rtl tends to be larger in terms of combinational logics, LUT, used. Usage of FFs, Mem, and ip core like dsp for multiply are similar. 50% to 100% higher. #HLS rtl also tends to do slower. I dont have manual crafted rtl to compare. This is…[Read more]
I have a modem module designed in matlab. Trying to port and test it on fpga these days. First generate c out of Matlab, then use ap fixed signal type to do floating to fixed point conversion. This usage of ap variable type is also required by Xilinx Vivado #HLS. Run sim…[Read more]
First #NB-IoT certification is announced in MWC 2018
MediaTek and ZTE have announced the industry’s first certification of NB-IoT R14 for commercial applications. By this announcement, the two companies actually suggest that the NB-IoT R14 specification is ready for the large-scale c…[Read more]
Using modular arithmetic to avoid timing overflow problems
The short version: Given a starting time start, an ending time end and an interval interval, the way to check whether the interval has elapsed is to use the expression end – start >= interval. The naive expression end >= start +…[Read more]
Wireless STM32 SoC supporting BLE 5 and IEEE 802.15.4 protocols
STM32WB Check out the new STM32WB, a dual-core multiprotocol wireless MCU. In this video Hakim explains the performance, size and cost advantages this product brings, including 2.4 GHz radio supporting BLE 5, brand and IP…[Read more]
If you get used to ARM architecture, this slides is a bit difficult to read since the interconnect fabric has ports with different name and therefore different functions. It is clear when you read the 2nd image. Turns out this fabric is not just interconnect.…[Read more]