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Recent Posts
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Reset ARM subsystem in Single Core and Multiple Core System May Not be Easy
Bill-Ramsey 02/11/2018 -
Optical phonons
ramkrishna 04/20/2018 -
ARM Cortex-M Processor Low Power
Bill-Ramsey 03/15/2018 -
Power Supply Connection in Low Power Design
Precise-Design 02/25/2018 -
Nanoscale Transistors
ramkrishna 04/20/2018
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An radio, wireless, and system design expert open to consultating
CHZhong 07/29/2016 -
Xilinx and Altera FPGA Expert
JingZh 04/21/2016
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Experienced Embeded and iOS/Androd Developer
Teddy 05/21/2016
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High Speed Digital Design Two-Day Workshop Handout
vonk 04/01/2016 -
Independent Firmware and System Consultant
JLee 02/02/2016
MikeD posted in
ASIC and FPGA 17 hours, 2 minutes ago · , 0, 0
[Read more]
jshukla posted in
Control, Robot, and AI 17 hours, 13 minutes ago · , 0, 0
Video how tesla is made by robots
[Read more]
himmatr posted in
Companies 17 hours, 41 minutes ago · , 0, 0
Check outbhow much tech companies pay
[Read more]
Schlenker posted in
IoT and Smart Devices 1 week, 3 days ago · , 0, 0
Arm drops Cordio IOT hardware IP and keeps #BLE software stack IP
https://www.eetimes.com/document.asp?doc_id=1334028&utm_source=eetimes&utm_medium=latestnews
chandran posted in
Control, Robot, and AI 1 week, 3 days ago · , 0, 0
Amazon launches smart plug controlled by Echo
Just say Alexa turn off living room light. It is done. No installation hassle.
[Read more]
JingZh posted in
ASIC and FPGA 1 week, 3 days ago · , 0, 0
How to force VHDL signal in simulation
Lack of signal force support in VHDL is really a headache to verification engineers. Unfortunately I ran into this issue recently. A signal in VHDL has to be forced in test bench or I have to hack VHDL which is obviously not desired. Amid quite a bit…[Read more]
Ravenhill posted in
Companies 2 weeks, 5 days ago · , 0, 0
Apple hiring to design ULP wireless chip
Apple is hiring in multiple sites including SV and SD to design low power radio chip. Rumor is it is about popular wifi and bluetooth. Are they going to ditch brcm as other ex-suppliers?
harrisonYu posted in
Companies 8 months ago · , 0, 0
Qualcomm big layoff?
IoT and server will be big hammered. Staff and senior staff levels will be more impacted. Other than 5g, all moves to india.
DivaK posted in
Companies 8 months, 1 week ago · , 0, 0
Apple ditches Intel chips in macs
Apple does it again. Use its own chips to replace third party’s. This time victim is I…[Read more]
JLarson posted in
ASIC and FPGA 8 months, 1 week ago · , 0, 0
Synopsys DC doesn’t optimize timing?
Get timing report from timing team. Surprise to see DC uses high delay cells which make the path failing the constraint by quite a bit. DC can easily use low delay cells to fix it. STA tool can fix it anyway. What really concerns me here is if DC takes…[Read more]
Sarkar posted in
ASIC and FPGA 8 months, 2 weeks ago · , 0, 0
#dft difference of #Synchronous #reset and async reset
Sync abd async reset have their pros and cons. Rtl point of view, one signal can be connected to both async reset and sync reset. This is not true for dft. You will see async reset has one extra dft mux on the sync reset to add in dft…[Read more]
Santos108 posted in
ASIC and FPGA 8 months, 2 weeks ago · , 0, 0
#Synthesis reports FFs without #clock?
Check your clock constraints if so. Most cases it is not rtl issue. FFs are connected to a clock. But this clock is not defined in clock constraints. Synthesis and STA treat it as no clock since no clock information is available.
Gloria posted in
Car Electronics 8 months, 2 weeks ago · , 0, 0
Does electrical car need wireless charging?
Nice to have. But how much radiation will it generate giving it is about 10KW energy transfer?
TrevorM posted in
ASIC and FPGA 8 months, 2 weeks ago · , 0, 0
#Fpga programing #spi #flash
The idea is to send data from pc to fpga and then from fpga to spi flash. Pc to fpga communication can be done with uart. Fpga then implements an spi master module which converts uart data to spi data sent to flash from spi master module.
In fact, lots of…[Read more]
earnestwu posted an update 8 months, 2 weeks ago · , 0, 0
#git
git is a widely adopted version control toolset. Some tips.
If you have a file locally changed and you want to merge with latest/HEAD in repo before add and commit to local repo, you can do
git stash
git pull
git stash pop
git stash pop will do merge for you.
If your local change…[Read more]
earnestwu posted an update 8 months, 2 weeks ago · , 0, 0
#Verilog, Part-select or indexed part-select cannot be applied to memory
Very annoying Verilog compiling error. Do you see anything wrong in below?
assign smpl_data[2:1] = 2’b0;
assign smpl_data[0] = 1’b1;
Turns out in some version of Verilog compile such as ncsim it is not allowed.…[Read more]
IAMMax posted in
Wireless 8 months, 2 weeks ago · , 0, 0
#LWA, aggregation of Mobile and wifi link
LWA (LTE/WLAN Aggregation) is a tight integration at radio level which allows for real-time channel and load aware radio resource management across #WLAN and #LTE to provide significant user perceived throughput (UPT) improvement. When enabling…[Read more]
KimJ posted in
RF and Optics 8 months, 2 weeks ago · , 0, 0
Ex Broadcom wireless heads are developing mobile 5G mmWave RFIC
They founded Movandi. Just unveil 28Ghz and 39Ghz RFIC for 5G.
PoojaV posted in
ASIC and FPGA 8 months, 2 weeks ago · , 0, 0
Synopsys buys kilopass to strengthen its IP pool
Kilopass offers one time programmable NVM. Synopsys is another big player in IP business other than ARM
[Read more]
MeganR posted in
Companies 8 months, 3 weeks ago · , 0, 0
#qualcomm ceo and others get low reelection vote and plan cost cut
Mollenkopf told investors following the company’s rejection of Broadcom’s bid that he could achieve earnings per share of $6.75 to $7.50 in fiscal 2019, through a number of measures, including a $1-billion cost red…[Read more]
mukhop posted in
Consumer Electronics 8 months, 3 weeks ago · , 0, 0
Google acquires Lytro for #VR imaging
[Read more]
Precise-Design posted an update 8 months, 3 weeks ago · , 0, 0
Use -y in verilog compilation
Modelsim and vcs support using -y to specify source file folders. You can use -v to list all the verilog files you want to compile. But here is an issue. If some of your tests dont need some files, you may want to remove these files from file list otherwise…[Read more]
mukhop posted an update 8 months, 3 weeks ago · , 0, 0
Another round of layoff just anounced. Surprise to most of us since product sells well. Senior and higher ranking guys are cut off more this time. Trim cost down and make room for youngers.
Now everyone is careful about their positions. Unwilling to share to make it harder to replace them.
minhlu posted in
Control, Robot, and AI 9 months ago · , 0, 0
Microsoft AI language translation can match human performance
Thats from chinese to english. Totally two different lang.
Another job replaced by AI
[Read more]
ENGITNOW posted in
IoT and Smart Devices 9 months ago · , 0, 0
Huawei opens HiLink to partners and plan to grow HiLink connected devices to $10Billion in three years.
Huawei is betting on smart home as others. But unlike Amazon and Apple, Huawei is not to release a smart speaker with AI voice assistance. Instead Huawei is betting on smart phone to be…[Read more]
himmatr posted in
Storage and Memory 9 months ago · , 0, 0
DRAM tutorial, including ddr5, lvddr, etc.
http://www.ece.umd.edu/~blj/talks/DRAM-Tutorial-isca2002.pdf
Brad_Smyth posted in
Embedded and Firmware 9 months ago · , 0, 0
ARM fast model
Built from ARM’s Fast Model toolkit, ARM provides a number of ready-to-use simulation models of platforms containing ARM processors, referred to asFixed Virtual Platforms. This OpenEmbedded Engineering Build is designed to work with a number of those FVPs which contain A…[Read more]
Brad_Smyth posted an update 9 months ago · , 0, 0
Need cpu to keep its sram state in power loss
Come up with this FRam based msp430. Perfect.
A new Compute Through Power Loss (CPTL) tool suite and library developed at Texas Instruments’ Kilby Labs enables the use of checkpointing on limited resource 16-bit MCUs. When an MCU’s ope…[Read more]
SD-RTL-DGN posted an update 9 months ago · , 0, 0
Pcie pme#, wake#
When system puts device into d3hot, it is possible that device wakes up itself due to detecting some event and wants to talk to system. How does device wake up system in this case?
Device can use beacon or wake# to wake up system. Wake# is a just a hw wire. On device side…[Read more]
ZakH posted an update 9 months ago · , 0, 0
Everyone has to start somewhere, Steve jobs’ job application
[Read more]
ZakH posted an update 9 months ago · , 0, 0
How many ipnone x can dudge a bullet?
JHicks posted in
ASIC and FPGA 9 months, 1 week ago · , 0, 0
Vivado #HLS finally works
Successfully used vivado HLS to synthesize cpp project into hw ip and havve it running on xilinx fpga. Note i said hw ip instead of rtl because generated rtl calls other xilinx cores which may further use other ips. There is NO file list to locate all the rtl…[Read more]
SD-RTL-DGN posted an update 9 months, 1 week ago · , 0, 0
Pcie bus master and msi
Bit2 of command reg in pcie config space specifies if device can initiate a pcie transaction or not. 1 means can.
Detail in https://wiki.osdev.org/PCI
In config space there is msi capability reg, msi address reg, and msi data reg. At enumeration, system software…[Read more]
kaamat posted in
ASIC and FPGA 9 months, 1 week ago · , 0, 0
Trying Vivado HLS II
Read some ref. HLS generated rtl tends to be larger in terms of combinational logics, LUT, used. Usage of FFs, Mem, and ip core like dsp for multiply are similar. 50% to 100% higher. #HLS rtl also tends to do slower. I dont have manual crafted rtl to compare. This is…[Read more]
kaamat posted in
ASIC and FPGA 9 months, 1 week ago · , 0, 0
Trying Vivado HLS
I have a modem module designed in matlab. Trying to port and test it on fpga these days. First generate c out of Matlab, then use ap fixed signal type to do floating to fixed point conversion. This usage of ap variable type is also required by Xilinx Vivado #HLS. Run sim…[Read more]
Dubey2016 posted in
IoT and Smart Devices 9 months, 1 week ago · , 0, 0
First #NB-IoT certification is announced in MWC 2018
MediaTek and ZTE have announced the industry’s first certification of NB-IoT R14 for commercial applications. By this announcement, the two companies actually suggest that the NB-IoT R14 specification is ready for the large-scale c…[Read more]
scottbalch posted in
ASIC and FPGA 9 months, 2 weeks ago · , 0, 0
Vivado #HLS and Altera hls for open-gl
Need to use hls to generate rtl and run on fpga. Seems both #xilinx and #Altera offers this hls tool. Altera tool taks in system design in open-gl. A comparison of these two:
Both can generate hardware for the example image processing algo with much…[Read more]
IanH posted an update 9 months, 2 weeks ago · , 0, 0
Using modular arithmetic to avoid timing overflow problems
The short version: Given a starting time start, an ending time end and an interval interval, the way to check whether the interval has elapsed is to use the expression end – start >= interval. The naive expression end >= start +…[Read more]
Egeberg posted in
Embedded and Firmware 9 months, 2 weeks ago · , 0, 0
Wireless STM32 SoC supporting BLE 5 and IEEE 802.15.4 protocols
STM32WB Check out the new STM32WB, a dual-core multiprotocol wireless MCU. In this video Hakim explains the performance, size and cost advantages this product brings, including 2.4 GHz radio supporting BLE 5, brand and IP…[Read more]
hOffutt posted in
MCU and DSP 9 months, 2 weeks ago · , 0, 0
AMD Zeppelin multiple core SoC
If you get used to ARM architecture, this slides is a bit difficult to read since the interconnect fabric has ports with different name and therefore different functions. It is clear when you read the 2nd image. Turns out this fabric is not just interconnect.…[Read more]