Xilinx Based 10G Ethernet MAC Design on Opencores

Make it to the Right and Larger Audience

Authors Zheng Cao
Date 2005
Affiliation Opencores
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Xilinx Based 10G Ethernet MAC Design on Opencores

This is a 10Gb Ethernet design based on Xilinx FPGA. It is a little bit old since it was done in 2005. But I find it still a good reference.

ethmac10g

 

 

Here is the rtl and bench codes:

.rtl_bench.zip

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