This page shows “Working With PLLs in PrimeTime”. It talks about using PLL to align intern clock and external clock phases. More like what JingZh talks about in use dcm and mmcm for xilinx fpga clock deskew in FPGA design. I never use this technique in ASIC design. But I do like how the author resolves the timing constraint issue in primetime. It also has good touch on some timing concepts such as clock jitter,OCV, and CRPR. OCV and CRPR are widely used in <65nm chip design. You got to take a look if you don’t know what they are. Article is well writen with good diagrams and PT reports.
Along the same line, page 2 shows “Constraining async clock domain crossings” and page 3 shows “Multiclock Propagation in Primetime”. Again there are more papers at the site. They even designed a Java tool to generate FSM RTL from GUI input, which sounds similar to Xilinx StateDiagram tool.