Key Words
IO IP, ESD, Latch-up, IO test and debugging
Brief
TakeCharge on-chip ESD protection up to 5V interfaces
When generic or foundry on-chip solutions for ESD do not meet your needs, TakeCharge® technology is the logical choice. Proven in thousands of ICs in commercial production, it offers a fast, reliable way to balance ESD protection with cost while enabling maximum IC performance.
Technical benefits
- Low parasitic capacitance for high speed or wireless interface protection: 100fF or lower
- Low leakage for analog interface protection
- Protect interfaces with most sensitive nodes like thin gates, core devices
Available
- Customized EOS/ESD solutions can be delivered within a few weeks for almost any CMOS node
- Proven in more than 50 foundry and proprietary technologies
- Reduce time to market by several months
Cost-efficient
- Silicon and product proven ESD solutions help to reduce IC development costs
- Smaller silicon footprint – reduce production cost by 1 to 10% through smaller dies
- Compatible with standard process flow – e.g. possible to skip ESD implant mask/step and save about 40$/wafer
