Digital IC layout, DFT
Digital ASIC Implementation and DFT Consultant
•Layout(physical implementation) of digital IC: RTL to GDSII
•Timing and power analysis
•Design for test solutions: setup test concept, DFT insertion, test vector generation.
•RTL and Timing Constraint validation
•Synthesis and Logic Equivalence Check
•FPGA Design and Implementation
•Ramp up of young engineer, start-up teams.