Verilog Initial Block Retriggering at Power up for RTL UPF Simulation

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Verilog Initial Block Retriggering at Power up for RTL UPF Simulation

Initial block is widely used in verilog modeling. Here is its basic syntax.



Valid_input is initialized to 1’b0 at simulation time 0. However, in RTL upf simulation, if macroA is assigned to a power domain which is not powered up at time 0, you will see above initial block is never executed, valid_input is never initialized to low and stay at x. This likely will mess up your simulation.


We can put in some verification code which detects macroA is powered up and then deposit low on valid_input. But this requires extra effort and is not a recommended solution. Simulation tool should be able to take care of it. Indeed if you use VCS NLP as RTL upf simulator, there is an easy way to retrigger verilog initial block at power up.


For above example, you can add below to your test bench.



This will reinitialize macroA_behave initial block each time it is powered up. Note “each time it is powered up” is critical since we want to initialize initial block not only at the 1st time the macro is powered up but also when the macro is out of power down sleep and power is reapplied to it.


You can refer to Synopsys VCS MX User Guide for  SNPS_reinit attribute detail.


Use the set_design_attributes command to enable initial block retriggering (reinit) on a design element. Following is the syntax of this command:

set_design_attributes -attribute SNPS_reinit -elements <element_list> -models <model_list> -transitive <TRUE|FALSE>

•<element_list> — List of design elements or named initial blocks.
•<model_list> — List of models to be attributed.

•-transitive <TRUE|FALSE> — When -transitive is TRUE, the command applies to the descendants of the elements. Default value is FALSE.


I think similar stuff exists for other simulators such as Modelsim and NCsim. If someone knows, feel free to share.


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  1. chieuluu 1 year ago


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    SD-RTL-DGN 1 year ago



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