Use UART for FPGA and SOC Debug

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Use UART for FPGA and SOC Debug

In lab we often need to use a PC to “talk” to the device under test. For example, we may want to write a register to kick off a state machine to start some processing. Then read registers for device status or read memories for processing result. We can also write memory with some input data before kick off the processing. All above can be done through a debug channel between PC and device under test.

 

A popular selection of this debug channel is UART. UART is easy to implement. There are lots of open source RTL code available. UART can support moderate baud rate which is good enough for debug purpose. There is also a good support of UART on PC side. For example, Tera Term is a popular PC application which can be used to control UART port.

 

In case of Xilinx FPGA, it is even easier. It just takes a couple of minutes to build a system like below. System consists of a Microblaze processor, an AXI interconnect, and an AXI uartlite module. Microblaze is a processor designed by Xilinx and Xilinx also supports ARM processors. AXI uartlite module talks to PC through UART. When uartlite receives data from PC, uarlite asserts interrupt to Microblaze. Firmware running on Mircoblaze then read data from uartlite and act on it. So in this example, firmware is needed to support uart debug.

 

Sometimes we don’t want firmware to get involved. Maybe it is because the system is pure data centric and doesn’t consist of a processor. The following diagram shows how to implement this hardware-only uart access approach. The example system is built around an AXI interconnect like above Xilinx example. Memory and registers each have an AXI slave port so they can be accessed from any AXI master. Uart module does uart tx/rx. Received data is passed to a module called “Data Processor”. It interprets uart data and generates address and write data which in turn are passed to AXI master module. AXI master starts AXI write or read transaction to memory or registers. In case of read, AXI master receives read data and passes it to uart which then sends it back to PC.

The following is a typical uart data format. Each box represents a 8-bit uart data. PC side first sends a signature which indicates the following data is for a debug transaction. This signature is optional. It is needed in case UART is used for other purpose. After signature, there is a command byte to indicate read or write. We can also implement burst read and write. After command it is a four-bype address assuming the system is of 32bit address. After address it is a four-byte write data assuming the memory and registers are of 32bit wide.

In case of read, Uart Tx data first has one or multiple bytes for flag indicating the following bytes are for debug access read data. This flag is optional as the signature on Rx side. Following Flag it is a four-byte read data.

 

 

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