This was a project I did before. We had 4 DSP processors to perform high speed image processing. Control and data hub is a high speed Virtex6 FPGA. There is also an SDRAM to buffer the data. Six components need to be inter-connected. So we tried star connection as shown in below Pspice model:
Fig 1. Pspice Model
where all 6 transmission lines are identical with Zo=50ohm and delay as 450ps. Delay of FR4 microstrip is 145ps/inch. So 450ps is about 3 inches. Voltage VPULSE source is set as V1=0, V2=1.8v, TR=TF=0.1ns, PW=15ns, and PER=30ns.
Sim shows with serial R11 as 45-55ohm, receiver side voltage is good as below.
Fig2. Receiver Waveform with R11=50ohm
But waveform distorts when we increase R11 to 90ohm (Fig3) and 180ohm(Fig4). Changing transmission line delay(aka length) didn’t help. Note DSP and Virtex6 driving strength is 10mA. For 1.8v IO, it is 1.8v/10mA=180ohm. On average it is 180/2=90ohm. So this result shows this topology doesn’t work. Main reason is R11 ofDSP and Virtext6 is too large so it takes a long time to charge all capacitance. We eventually dropped this idea. Share this lesson to show you how we used Pspice model to reveal board design issue BEFORE board was built.
Fig23. Receiver Waveform with R11=90ohm
Fig4. Receiver Waveform with R11=180ohm
If you are interested to give it a try yourself, Pspice schematics file of Fig 1 is attached.