Stan Hay has a good blog about How to Integrate Third-Party IP Hard Macro into Xilinx FPGA
I had similar experience before. Here is some of my experience.
Let’s say you are working on an FPGA project and you have an IP core designed and delivered by a third party. To protect their IP, third party may deliver their core in compiled version (netlist) rather than source code. A netlist delivered by third party normally contains edif file and vhd file. Edif file is to be used in synthesis and vhd is for simulation. Let’s say this delivery targets some specific type of Xilinx FPGA. Then edif goes down to primitive level such as RAM128x1D and LUT. (So this netlist is not good for asic) Vhd also goes down to primitive level. The RAM128x1D simulation model which is referenced in vhd file is in Xilinx unisim library.
In modelsim_xe/Xilinx/vhdl/src/unisims/unisim_vital.vhd, you can find behavioral model of RAM128x1D. Unisim_vital.vhd is already compiled in modelsim_xe/Xilinx/vhdl/unisim and can be used across projects.
Above edif is likely generated by Synplify pro. If netlist is generated by Xilinx ISE, likely you will get ngc or ngd netlist instead of edif.
Let’s say a netlist uses a FIFO core which is generated by Xilinx Coregen. Coregen generates ngc(or edif), vhd, and vho files. Vhd is just an template which saves you some time when you instantiate this module. Vho is a simulation model and should be used in your simulation. This vho may further use a model in xilinxcore library as model_xe/Xilinx/vhdl/src/xilinxcorelib/<model.vhd>. You can find beh model of this core in this file. This vho can’t be used in ise synthesis. It has something like “–synthesis translate on” and “–synthesis translate off” which causes this model empty in ISE synthesis)
So you have a large design which uses several coregen cores, some 3rd party netlists, and some RTL files in verilog. You run Xilinx ISE synthesis and translate on the design. At the end of translation, you get an ngd file. This ngd file is for the whole design. Ngd is like edif and is a netlist file. You can instruct ise to generate edif rather than ngd. You can also instruct ise to generate an after-synthesis simulation model for this design. This simulation model should use unisim primitive models and xilinxcorelib models. (For all the coregen cores in the design, the generated sim model just reference coregen cores. And in simulation project, user needs to specify sim model for the coregen core which is in xilinxcorelib)
Let’s say you have a design which contains a top module top.vhd which further instantiates two coregen cores, core1 and core2, and other logics. Ise synthesis will generate a ngc file for top module. Note this ngc doesn’t include netlist for coregen core1 and core2. Then at translate stage, ise combines three ngc files, top.ngc, core1.ngc, and core.ngc with other ngc or edif files to generate top.ngd for the whole design.
So translate generates one ngd file and this ngd has all the connections. At translate stage, you can generate after-translate simulation model. You won’t see core1 and core2 but only see primitives under core1 and core2. All models here are from simprim library. To compare, after-synthesis sim model (netgen/synthsis/top_synthesis.vhd) has core1 and core2 and these two cores use xilinxcorelib model.
So coregen cores are not primitives but one layer above primitives (like RTL logic) but Xilinx does not provide source code and just netlist (ngc or edif) and simulation model. Primitive is like standard cell target library in asic design.