Use Cordic to Implement DDS with Verilog Code

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Use Cordic to Implement DDS with Verilog Code

Cordic based DDS is based on the previous post in this series that uses Cordic to calculate sine and cosine of an arbitrary angle. The difference is in previous post, we have one cordic core and it is reused 16 times to do the 16 iterations with the penalty of slow throughput. To implement DDS, we need an output per clock cycle. So instead of time-sharing one core, we implement 16 cores and use pipelining to generate sine output per clock cycle.

Here is the m code to prepare the parameters:

 

Here is the result when running above m-code:

cordic_dds_m

Here is simulation output and we set x/y output to use analog format. So they have sin/cos wave shape as expected.

cordic_dds

Here is the zip file for full verilog code, tb, and m code:

.cordic_dds.zip

 
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3 Comments
  1. manhduc1811 2 weeks ago
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    Dear Mr. Juan Tang,

    Thank you so much for sharing CORDIC algorithm in Verilog, it helps me so much.
    However, I have some concerns about #2 of your CORDIC series.
    Mostly, I understand all what you mean there, but there are 2 main things I am not exactly know, I hope you can explain more.

    1) In Cordic CORE:
    why wire [ANG_WIDTH-1:0] z_t = z_i – 16’d16384; ???
    ~~ 16384 = 2*28192 = 2*2*4096.
    2) In Cordic CORE:
    always @ (posedge clk)
    begin
    x_o <= (x_t[VEC_WIDTH])?((x_t[VEC_WIDTH-1]==1'b1)?x_t[15:0]:16'h8001):((x_t[VEC_WIDTH-1]==1'b0)?x_t[15:0]:16'h7FFF);
    y_o <= (y_t[VEC_WIDTH])?((y_t[VEC_WIDTH-1]==1'b1)?y_t[15:0]:16'h8001):((y_t[VEC_WIDTH-1]==1'b0)?y_t[15:0]:16'h7FFF);
    end

    Actually, I found one mistake, I correct it and just confirm you:
    in DDSCordic:
    always @ (posedge clk, negedge clk)

    BRs,
    mducng

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  2. alexsdsd69 7 months ago
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    nice

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  3. earnestwu 5 years ago
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    Thanks! The code all works on my side. Good reference to get me started using Cordic.

    5

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