UPF and Retention

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UPF and Retention

This post is intended for low power design starters and answer some basic questions:

  1. retention flip flop is supposed to hold flip flop content. why do I see ret FF outputs becomes ‘x’ in sim in retention mode?
  2. when ret FF output is out of ‘x’? is it when main pwr is re-applied or when retention condition (specified in UPF) is not met?
  3. I have a power supply net which is partial on. Does it cause retention FF to loose its content?
  4. How can I change my power supply net to be full on?
  5. What is relationship between supply set is NORMAL or CORRUPT and supply net is full_on, partial_on, off, etc?


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We are a small team of ASIC and FPGA design engineers with combined >40 years of experience. We successfully led several chips through the whole design to TO process. Familiar with Xilinx FPGA, we designed complicated system of using multiple FPGAs to verify complicated ASIC and also for the final products. We are interested in working as independent contractor for your projects. Feel free to contact us.


1 Comment
  1. DRama 3 years ago

    Good explaining


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