Rhoney has a good intro about glitch free clock muxing. The fundamental circuit is shown as below.
I have it implemented and it works well except two potential issues.
First, let’s say clock mux is currently selecting CLK1. If we’d like to switch from CLK1 to CLK0, CLK1 can NOT be off. It is easy to understand. It is due to the sync FF. If CLK1 is off, sync FFs on CLK1 will not toggle and this will block CLK0 to be turned on. This can be inconvenient for some digital designs. Clocks are preferred to be gated off to save power consumption. Designer needs to make sure clock is there to be able to switch to the other clock.
Is it the same issue if the target clock does not toggle? Well, yes. Sync FFs on target clock will be toggle which will also block switching. But even the circuit can switch to it, it is just static and not much different from current way. As long as source clock toggles, clock muxing output will be 0 in this case since source clock path is turned off.
Second issue is more tricky. This circuit is supposed to be glitch free but its output can be glitchy under some condition. I happen to see the issue in simulation. In my setup, CLK0 is quite slow compared to CLK1. CLK1 is first selected, then CLK0, and finally back to CLK0. But sim shows glitchy output. How can it be? Well, it turns out CLK1->CLK0->CLK1 switching happens too fast relative CLK1 and CLK0 clock cycles. This glitch free circuit has a limitation that the SELECT signal can not toggle too fast, relative to CLK1 and CLK0 cycles, to make sure the two synchronizers on CLK0 and CLK1 can finish synchronization. Otherwise output can be glitchy.
This fact reminds me a paper I read long time ago. It talks about synchronization. A quiz. Does two FF based synchronizer always work? No. The input to synchronizer can not toggle too fast otherwise transitions will be missed.