Two Issues Seen when Inserting BIST Logic In an SoC with Multi Power Domains

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Two Issues Seen when Inserting BIST Logic In an SoC with Multi Power Domains

Mbist is employed to conduct memory test on tester. Below diagram is a generic structure of how memory BIST logic is connected to memory. How memory BIST works can be a big and lengthy topic. This article focuses on two issues could be seen if MBIST logic is employed in conjunction with low power SoC design with multiple power domains and the solutions.


Memory BIST logic is normally inserted by DFT tool and not present in RTL code. An RTL design with a memory is shown in below diagram.


It is possible that SRAM and the surrounding logic are not in the same power domain. For example, SRAM can save critical content which needs to be retained during power down sleep. To cut sleep current, the surrounding logic may need to be powered down during power down sleep. In this case, SRAM is relatively more powered-on than the surrounding logic and isolation cells need to be inserted on signals going from surrounding logic to SRAM.



Next we will show how this could go wrong and how to resolve it. We will discuss another issue how to properly isolate signals between DFT logic and function logic.


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Highlights: 877 words, 3 images
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  1. chieuluu 1 year ago


  2. rao_mallikarjun 1 year ago

    how the UPF will e added

  3. rao_mallikarjun 1 year ago

    good article


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