Recently we have an interesting yet ugly issue. The design is like below:
As simple as it can be. Module a and module b talk to each other. Their clocks come from the same source and by design two clocks need to be synchronized. There is no synchronizer inside either module. But unfortunately timing constraint has two clocks specified as ASYNC. So obviously this circuit does not work. But this is ASIC. Re-spin a chip is very costly and timing consuming. It is very important if we can work-around this issue and continue testing the chip. There could be other issues to be found and fixed before the next chip spin. You don’t want to do a round of spin for each issue you have. Otherwise it is better for you to quit hardware and become a firmware engineer.
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