First, there are two good articles about source synchronization.
- AN 433: Constraining and Analyzing Source-Synchronous Interfaces from Altera
- Source-Synchronous Clock Designs: Timing Constraints and Analysis from Microsemi
The 2nd article uses a system built out of a FPGA and a ASIC to illustrate source synchronization concept. If system follows “single common clock topology” as shown in below, since the same clock goes to both FPGA and ASIC, it is possible to meet timing in ASIC so no source synchronization is needed.
But if FPGA and ASIC uses two different clocks, source synchronous is needed which means FPGA needs to send clock along with data to ‘sink’ endpoint in ASIC.
It is a valid point. It is possible to use hand-shaking synchronization to correctly send data but it is slow due to cross-clock domain hand-shaking and is not a good solution for high data rate data. Source synchronization is preferred solution.
But source synchronization can also help in “single common clock topology”. Due to different delays on FPGA clock and ASIC clock, clock phases of source endpoint in FPGA and sink endpoint in ASIC can be quite different. Although sometime it is possible to manually adjust clock phase to make it work, source synchronization can be a good alternation.
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