Timing Constraint Example: Clock Mux and Clock Divider

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Timing Constraint Example: Clock Mux and Clock Divider

Above we have a clock mux. First we need to define clk1 and clk2. Assuming they are root/source clocks we can use create_clock:

Next we can define their relationship to be asynchronous:

Another way is to use the old-school set_false_path to specify paths from clk1 to clk2 and vice versa are asynchronous. But if you have many clocks set_clock_groups are much more efficient.

If clk1 and clk2 only goes to this clock mux and do not drive other logics, we can also specify clk1 and clk2 to be exclusive to allow tool to take advantage of this information in timing closure.


No need to define clk3.

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