Technical Brief of Two Qualcomm Patents that Apple found infringed

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Technical Brief of Two Qualcomm Patents that Apple found infringed

On March 15th, a jury of federal court in CA found Apple infringed three Qualcomm patents.

The iPhone models involved in the patent suit are iPhone 7, 7 Plus, 8, 8 Plus and X, which were found to infringe two Qualcomm patents, U.S. Patent No. 8,838,949 (“flashless booting”), and U.S. Patent No. 9,535,490 (data management between the applications processor and the modem); and the iPhone 8, 8 Plus and X which were found to infringe Qualcomm’s U.S. Patent No. 8,633,936 (high performance rich visual graphics with power management).

Put the fights between two goliaths aside, as a firmware engineer, I am curious about what the patents are about. Here the key ideas of the first two patents are briefly introduced. This is just my interpretation though. Hope it help others because reading patent is not fun, at least not to me.


US8,838,949B2, Direct scatter loading of executable software image from a primary processor to one or more secondary processor in a multi-processor system


The system, as shown below, consists of two processors, primary proc and secondary proc. In case of iphone and ipad, primary proc is the A-series application processor designed by Apple and 2nd proc can be the arm-based processor reside in modem chip. Two processors are normally not on the chip. Primary processor has the associated non-volatile memory such as flash and volatile system memory such as dram or sram. 2nd proc needs its own volatile system memory for run-time processing. 2nd proc may also have its own non-volatile memory but even so it is small to save cost. 2nd proc’s firmware therefore is saved inside primary processor’s non-volatile memory.

The goal is how to download fw image from non-volatile memory of pri proc to system memory of 2nd proc.


The patent claims traditionally it is a two-step process. First the whole image is downloaded from pri proc side but buffered in a temporary buffer in 2nd proc system memory. Next the image in buffer is scatter loaded into target areas in 2nd proc system memory. It is not efficient due to mem to mem copy happening in 2nd proc system memory.

The patent provides means to remove the above mem-to-mem copy for image download. Below shows two ways proposed by the patent. Note the patent tends to cover all the small variations so the following two ways are just some typical flows to show the key idea of the patent and they are not the full coverage.


Both ways assign image header to firmware image to be downloaded. Image header has size of firmware image information and where fw image is located in pri proc system memory. It may also contain information where fw image should be downloaded to in 2nd proc system memory.

Both ways also take advantage of the existence of scatter load controller (block 304 in diagram). Scatter load controller is just a DMA engine which moves data from one piece of memory to another piece. Two memories can exist on different chips.


The first way is a four-step process.

  1. image header and image data segments are copied from non-volatile memory to volatile sys memory on pri proc side. This is normally needed and DMA engine is not efficient in handling non-volatile memory access.
  2. image header is sent to 2nd processor.
  3. 2nd proc processes the image header. Based on extract information such as image size, image location in pri proc sys mem, and targeted areas in 2nd proc sys mem, 2nd  proc programs scatter load controller.
  4. Scatter load controller then downloads fw image from pri proc sys mem to 2nd proc sys mem.



The 2nd way is also a four-step process.

  1. Same as in the first way. Image header and image data segments are copied from non-volatile memory to volatile sys memory on pri proc side.
  2. Pri proc reads and parses the image header.
  3. Pri proc programs scatter load controlled based on parsed image header.
  4. Same as in the first way. Scatter load controller downloads fw image from pri proc sys mem to 2nd proc sys mem.


Not complicated, right? If you think this patent is simple and straightforward, wait until you see the 2nd one.


US9535490B2, Power saving techniques in computing devices.


Application processor and modem processor need to exchange data. The data rate is normally high due to multimedia contents and therefore high speed link such as PCIe is normally used. The issue this patent tries to deal with is to put system in low power state as much as possible. High speed link warm up overhead can be long so high speed link is good for large volume data transfer and it is not efficient to wake up often and just transfer a small amount of data each time. Same is true on pri-processor and 2nd proc side. Each side sleep wake up time is not negligible. Each side is preferred to stay in low power state for as long as possible and not disturbed by small amount of data.


You may already figure out a solution. As far as latency is acceptable, why not each side buffers data first and only wakes up link and the processor on the other side when data reaches certain level. Well, this is pretty much what the patent is about. Only difference is instead of checking if data reaches certain level, the patent proposes to use a timer to buffer data within a period of time. When timer expires, send the data to the other side. Or when it receives data from the other side, since the link and two processors are up, also sends data to the other side. Straightforward, right? Now you understand why Qualcomm’s patents are so difficult to bypass.



Author brief is empty

  1. btiaz 2 years ago

    I do think the boot method introduced in the 1st patent is what have been doing for years. Damn, didnt know it is patented

  2. mrgice 2 years ago

    Nice explaining!


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