Tech Posts

Make it to the Right and Larger Audience

Tech Posts

Share and Influence

Verilog Initial Block Retriggering at Power up for RTL UPF Simulation

Parker, 12/08/2019 2

ASIC and FPGA

simulation. low power, upf

4.5 4.5/5 (2 )

Memory Function Path ATE Testing

Wayland Chen, 12/08/2019 1

ASIC and FPGA

ATPG, dft, memory

5 5/5 (1 )

Crystal safety margin test and crystal startup time reduction

VinayClark, 12/07/2019 1

Analog, Mixed, and Power, ASIC and FPGA, IoT and Smart Devices

Crystal, xtal

5 5/5 (1 )

Does it matter if async reset deassert edge is not synced and Should we check async reset timing in timed GLS P

Precise-Design, 12/06/2019 0

ASIC and FPGA

reset

ASIC Memory Low Power: Memory Standby Mode and Memory Clock Gating

Degg12, 12/04/2019 2

ASIC and FPGA

memory, power, standby

3.5 3.5/5 (2 )

ASIC Memory Low Power: Single Rail, Split Rail, and Low Power Modes

Degg12, 12/04/2019 1

ASIC and FPGA

memory, power

3 3/5 (1 )

Case study: how DFT output dedicated isolation cell causes issue in Burn-In test V

AnkitKumar, 12/03/2019 2

ASIC and FPGA

burnin, dft

4.5 4.5/5 (2 )

Transmission Gate Not to be Used on Voltage Domain Boundary P

JLarson, 12/03/2019 1

ASIC and FPGA

leakage, transmission gate

4 4/5 (1 )

SoC IO Pad, Bump, Ball, and Pin

entcag, 09/22/2019 2

ASIC and FPGA

package

3.5 3.5/5 (2 )

Use VCLP and UPF to report power domain crossing signals

PoojaV, 09/18/2019 1

ASIC and FPGA

upf, vclp

4 4/5 (1 )

Body Biasing and PFET Nwell Connection

FRANH, 09/10/2019 0

ASIC and FPGA

power, standard cell

Case study: how to insert logic on cross hardmacro signal properly with power domain consideration P

Precise-Design, 09/09/2019 1

ASIC and FPGA

isolation, power

3 3/5 (1 )

Discussion of ” A simple way to estimate the total power consumption of memories in an SoC”

Yicheng, 09/09/2019 0

ASIC and FPGA

memory, power

Isolation Low and High Cells for SoC Low Power Design V

peterSze, 09/07/2019 1

ASIC and FPGA

isolation, low power

3 3/5 (1 )

Issues and Solutions of Formality Formal Verification for Beginners

LarryB, 08/19/2019 5

ASIC and FPGA

Formal, formal verification, Formality

5 5/5 (2 )

Several Techniques to Reduce Memory Block Current Consumption V

Arcis, 08/18/2019 3

ASIC and FPGA

memory, power

4 4/5 (1 )

BLE HADM Basic and Usage for Keyless Entry

wlsPark, 08/18/2019 5

IoT and Smart Devices, Wireless

BLE, bluetooth, HADM

4.5 4.5/5 (4 )

PEM and OBIRCH, Bright Spot Failure Analysis for Flip Chip

nedge, 08/17/2019 0

ASIC and FPGA

FA, failure, OBIRCH, PEM

An Intrinsically Secure Processor and A Software Based Security Approach

elwood-speth, 08/16/2019 2

ASIC and FPGA, MCU and DSP

memory, security

5 5/5 (1 )

Memory Tag Extension (MTE) in Armv8.5-A

Halidon, 08/11/2019 1

ASIC and FPGA, Embedded and Firmware

memory, MTE, overflow

LBIST and MBIST

jshukla, 08/10/2019 1

ASIC and FPGA

dft, lbist, mbist

5 5/5 (1 )

Two Potential Issues with Glitch Free Clock Muxing

Trydeman, 08/08/2019 3

ASIC and FPGA

clock, synchronization

3 3/5 (2 )

What are some creative uses of the Raspberry Pi?

shenzhengrande, 08/06/2019 2

IoT and Smart Devices, Networking and Interconnect, Test and Measurement

#PCBSize #PCBManufacturing #PCBA #EMS #RaspberryPi #Electronics

5 5/5 (1 )

What are some semiconductor devices?

shenzhengrande, 08/06/2019 0

Industrial Control, IoT and Smart Devices, PCB and Board Design

#58pcba #Semiconductor #EMS #ElectronicsManufacturing #PCB #PCBA

Transmission Gate Not to be Used on Voltage Domain Boundary P
JLarson 12/03/2019 4 4/5 (1 )

My other post, Transmission Gate and the Sneaky Leakage Path, discusses transmission gate should not used at power...
ASIC Memory Low Power: Single Rail, Split Rail, and Low Power Modes
Degg12 12/04/2019 3 3/5 (1 )

This is post #1 of 2 in the series “ASIC Memory Low Power” ASIC Memory Low Power Memory power...
SoC IO Pad, Bump, Ball, and Pin
entcag 09/22/2019 3.5 3.5/5 (2 )

It could be confusing to beginners what are ball, bump, pad, and pin in chip design. Hope this doc...
Memory Function Path ATE Testing
Wayland Chen 12/08/2019 5 5/5 (1 )

Memory BIST is well known and widely used to test on-chip memories. However, Mbist does not use function path....
Use VCLP and UPF to report power domain crossing signals
PoojaV 09/18/2019 4 4/5 (1 )

In vclp shell, run below command report_crossover and it will report...
Case study: how DFT output dedicated isolation cell causes issue in Burn-In test V
AnkitKumar 12/03/2019 4.5 4.5/5 (2 )

This is post #3 of 3 in the series “some DFT topics” some DFT topics Recently our chip burn-in...
Does it matter if async reset deassert edge is not synced and Should we check async reset timing in timed GLS P
Precise-Design 12/06/2019

This post is triggered by Ravenhill’s question Does it really matter if async reset’s deasset edge is not synced?...
ASIC Memory Low Power: Memory Standby Mode and Memory Clock Gating
Degg12 12/04/2019 3.5 3.5/5 (2 )

This is post #2 of 2 in the series “ASIC Memory Low Power” ASIC Memory Low Power UMC 40nm...
Crystal safety margin test and crystal startup time reduction
VinayClark 12/07/2019 5 5/5 (1 )

There are two common issues with usage of crystal. Crystal oscillation becomes unstable with the aging of crystal or...
Verilog Initial Block Retriggering at Power up for RTL UPF Simulation
Parker 12/08/2019 4.5 4.5/5 (2 )

Initial block is widely used in verilog modeling. Here is its basic syntax. module macroA_behave reg valid_input; initial...

Contact Us

Thanks for helping us better serve the community. You can make a suggestion, report a bug, a misconduct, or any other issue. We'll get back to you using your private message ASAP.

©2020 ValPont.com