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Does it matter if async reset deassert edge is not synced and Should we check async reset timing in timed GLS
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Precise-Design 12/06/2019This post is triggered by Ravenhill’s question Does it really matter if async reset’s deasset edge is not synced?...
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ASIC Memory Low Power: Single Rail, Split Rail, and Low Power Modes
Degg12 12/04/2019This is post #1 of 2 in the series “ASIC Memory Low Power” ASIC Memory Low Power Memory power...
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SoC IO Pad, Bump, Ball, and Pin
entcag 09/22/2019It could be confusing to beginners what are ball, bump, pad, and pin in chip design. Hope this doc...
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Use VCLP and UPF to report power domain crossing signals
PoojaV 09/18/2019In vclp shell, run below command report_crossover and it will report...
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Crystal safety margin test and crystal startup time reduction
VinayClark 12/07/2019There are two common issues with usage of crystal. Crystal oscillation becomes unstable with the aging of crystal or...
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Memory Function Path ATE Testing
Wayland Chen 12/08/2019Memory BIST is well known and widely used to test on-chip memories. However, Mbist does not use function path....
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Case study: how DFT output dedicated isolation cell causes issue in Burn-In test
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AnkitKumar 12/03/2019This is post #3 of 3 in the series “some DFT topics” some DFT topics Recently our chip burn-in...
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Transmission Gate Not to be Used on Voltage Domain Boundary
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JLarson 12/03/2019My other post, Transmission Gate and the Sneaky Leakage Path, discusses transmission gate should not used at power...
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Verilog Initial Block Retriggering at Power up for RTL UPF Simulation
Parker 12/08/2019
Initial block is widely used in verilog modeling. Here is its basic syntax. module macroA_behave reg valid_input; initial...
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ASIC Memory Low Power: Memory Standby Mode and Memory Clock Gating
Degg12 12/04/2019This is post #2 of 2 in the series “ASIC Memory Low Power” ASIC Memory Low Power UMC 40nm...
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