DFT JTAG and ARM JTAG Security
This is post #4 of 4 in the series “ARM and DFT JTAG” ARM and DFT JTAG discussion DFT...
Cadence HLS Stratus IDE Basic: How to Use the Example FIR Project
This is post #1 of 3 in the series “Cadence HLS Stratus” Cadence HLS Stratus High level synthesis (HLS)...
DFT Scan Shift Current for IR Drop Analysis
When we do IR drop analysis, we would like to use the worst case current. The next question is...
OWE (Overall Wafer Effectiveness) and MFU (Mask Field Utilization)
OWE (Overall Wafer Effectiveness) and MFU (Mask Field Utilization) are two closely related terms and both are about how...
ASIC RC Corners or Parasitic Interconnect Corners
For ASIC timing closure lots of us know we need to check PVT corner. In deep submicron technology node,...
Cadence HLS Stratus: Analysis of FIR Example Project
This is post #2 of 3 in the series “Cadence HLS Stratus” Cadence HLS Stratus This post will take...
TrustZone, MultiZone, Security Check and Code Signing
MultiZone security proposed by Hex Five for RISC-V is compared with ARM’s trustZone in my other post, Hex Five’s...
Transfer of High Rate Data With Source Synchronous and Other Methods
This is post #5 of 5 in the series “Clock and Synchronization” Clock and synchronization First, there are two...
Some Considerations of ASIC Clock CTS and STA
Let’s say a design has three clocks, clk1, clk2, and clk3. They are synchronous to each other. The Blog...
Cadence HLS Stratus: ecoFlow
This is post #3 of 3 in the series “Cadence HLS Stratus” Cadence HLS Stratus Cadence Stratus IDE comes...