Tech Posts

Make it to the Right and Larger Audience

Tech Posts

Share and Influence

SoC IO Pad, Bump, Ball, and Pin

entcag, 09/22/2019 0

ASIC and FPGA

package

Use VCLP and UPF to report power domain crossing signals

PoojaV, 09/18/2019 0

ASIC and FPGA

upf, vclp

Body Biasing and PFET Nwell Connection

FRANH, 09/10/2019 0

ASIC and FPGA

power, standard cell

Case study: how to insert logic on cross hardmacro signal properly with power domain consideration P

Precise-Design, 09/09/2019 0

ASIC and FPGA

isolation, power

Discussion of ” A simple way to estimate the total power consumption of memories in an SoC”

Yicheng, 09/09/2019 0

ASIC and FPGA

memory, power

Isolation Low and High Cells for SoC Low Power Design V

peterSze, 09/07/2019 0

ASIC and FPGA

isolation, low power

Issues and Solutions of Formality Formal Verification for Beginners

LarryB, 08/19/2019 4

ASIC and FPGA

Formal, formal verification, Formality

5 5/5 (1 )

Several Techniques to Reduce Memory Block Current Consumption V

Arcis, 08/18/2019 2

ASIC and FPGA

memory, power

BLE HADM Basic and Usage for Keyless Entry

wlsPark, 08/18/2019 2

IoT and Smart Devices, Wireless

BLE, bluetooth, HADM

4.5 4.5/5 (2 )

PEM and OBIRCH, Bright Spot Failure Analysis for Flip Chip

nedge, 08/17/2019 0

ASIC and FPGA

FA, failure, OBIRCH, PEM

An Intrinsically Secure Processor and A Software Based Security Approach

elwood-speth, 08/16/2019 1

ASIC and FPGA, MCU and DSP

memory, security

Memory Tag Extension (MTE) in Armv8.5-A

Halidon, 08/11/2019 1

ASIC and FPGA, Embedded and Firmware

memory, MTE, overflow

LBIST and MBIST

jshukla, 08/10/2019 0

ASIC and FPGA

dft, lbist, mbist

Two Potential Issues with Glitch Free Clock Muxing

Trydeman, 08/08/2019 2

ASIC and FPGA

clock, synchronization

1 1/5 (1 )

What are some creative uses of the Raspberry Pi?

shenzhengrande, 08/06/2019 1

IoT and Smart Devices, Networking and Interconnect, Test and Measurement

#PCBSize #PCBManufacturing #PCBA #EMS #RaspberryPi #Electronics

What are some semiconductor devices?

shenzhengrande, 08/06/2019 0

Industrial Control, IoT and Smart Devices, PCB and Board Design

#58pcba #Semiconductor #EMS #ElectronicsManufacturing #PCB #PCBA

RTL Hardware Design with Operation Chart instead of State Flow Chart V

XaviM, 08/06/2019 0

ASIC and FPGA

controller, RTL

Two Issues Seen when Inserting BIST Logic In an SoC with Multi Power Domains V

Palak_Nair, 08/04/2019 2

ASIC and FPGA

dft, low power

SoC Non-Intrusive Tracing for Debugging, Profiling, and Security Monitoring

Silverman, 07/30/2019 1

ASIC and FPGA

debug, profiling, security

5 5/5 (1 )

Hex Five’s MultiZone Security for RISC-V

Egeberg, 07/29/2019 1

MCU and DSP

RISC-V, security

4 4/5 (1 )

ASIC Interview Questions at A****

Trek23, 07/27/2019 0

ASIC and FPGA, Graduate

interview

ROM Conventional and Shared Bit Lines Structures

NingL, 07/24/2019 0

Analog, Mixed, and Power, ASIC and FPGA

memory, Rom

ARM CoreSight for Cortex Processor Based SoC V

Silverman, 07/10/2019 0

ASIC and FPGA, Embedded and Firmware

arm, cortex, debug

PCIE Tutorial: PCIE Error S

SD-RTL-DGN, 07/09/2019 0

ASIC and FPGA

error, PCIE

Body Biasing and PFET Nwell Connection
FRANH 09/10/2019

What is body and substrate biasing? How to connect PFET nwell? It is supposed to be a simple topic...
BLE HADM Basic and Usage for Keyless Entry
wlsPark 08/18/2019 4.5 4.5/5 (2 )

In Nov 2018, Belgium IMEC demonstrated the first solution for secure and very accurate passive keyless car entry based...
Isolation Low and High Cells for SoC Low Power Design V
peterSze 09/07/2019

Isolation cells are a must-use for SoC low power design. This article covers: Schematics of source type and destination...
Issues and Solutions of Formality Formal Verification for Beginners
LarryB 08/19/2019 5 5/5 (1 )

I recently met a couple of issues when running formality to check equivalence of RTL vs synthesized netlist. I...
Discussion of ” A simple way to estimate the total power consumption of memories in an SoC”
Yicheng 09/09/2019

There is a short blog about memory current estimation, A simple way to estimate the total power consumption of...
SoC IO Pad, Bump, Ball, and Pin
entcag 09/22/2019

It could be confusing to beginners what are ball, bump, pad, and pin in chip design. Hope this doc...
Several Techniques to Reduce Memory Block Current Consumption V
Arcis 08/18/2019

On chip embedded memory is a critical building block of a System on Chip (SoC). It not only occupies...
Case study: how to insert logic on cross hardmacro signal properly with power domain consideration P
Precise-Design 09/09/2019

This is post #12 of 12 in the series “UPF and low power” UPF and low power In Case...
Use VCLP and UPF to report power domain crossing signals
PoojaV 09/18/2019

In vclp shell, run below command report_crossover and it will report...
PEM and OBIRCH, Bright Spot Failure Analysis for Flip Chip
nedge 08/17/2019

Photon Emission Microscopy (PEM) and optical beam induced current change (OBIRCH) are high efficient failure analysis techniques for fault...

Contact Us

Thanks for helping us better serve the community. You can make a suggestion, report a bug, a misconduct, or any other issue. We'll get back to you using your private message ASAP.

©2019 ValPont.com