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Transfer of High Rate Data With Source Synchronous and Other Methods S

SD-RTL-DGN, 03/23/2020 0

ASIC and FPGA

clock, synchronization

Some Considerations of ASIC Clock CTS and STA

KevinP1, 03/22/2020 0

ASIC and FPGA

Backend, clock, cts, STA

ASIC RC Corners or Parasitic Interconnect Corners

KevinP1, 03/19/2020 0

ASIC and FPGA

Backend, Interconnect, timing

OWE (Overall Wafer Effectiveness) and MFU (Mask Field Utilization)

QYang, 03/17/2020 0

ASIC and FPGA

Backend, Foundry

Cadence HLS Stratus: ecoFlow

BrandonG, 03/17/2020 0

ASIC and FPGA

HLS, Stratus, SystemC

DFT JTAG and ARM JTAG Security S

SD-RTL-DGN, 03/15/2020 0

ASIC and FPGA

arm, dft, JTAG, security

TrustZone, MultiZone, Security Check and Code Signing

Egeberg, 03/15/2020 0

ASIC and FPGA

security, trustzone

DFT Scan Shift Current for IR Drop Analysis

Angpol, 03/14/2020 0

ASIC and FPGA

dft, IR drop

Cadence HLS Stratus: Analysis of FIR Example Project V

BrandonG, 03/12/2020 0

ASIC and FPGA, Wireless

HLS, Stratus, SystemC

Cadence HLS Stratus IDE Basic: How to Use the Example FIR Project

BrandonG, 03/11/2020 0

ASIC and FPGA, Wireless

HLS, Stratus, SystemC

How Long an Input Pad Needs to be Asserted for a Chip to See it?

SJean, 03/02/2020 0

ASIC and FPGA, PCB and Board Design

GPIO, interrupt

Deal with X at the Beginning and in the Middle of Simulation

cluster010, 02/29/2020 0

ASIC and FPGA

verification, x pessimism

Thoughts about integrating DSP into Data Process Chain

wyuan, 02/29/2020 0

ASIC and FPGA

dsp

An SoC Design for Data Streaming V

wyuan, 02/29/2020 0

ASIC and FPGA

soc, streaming

ASIC Die Size Estimation Due to Change of Process

Arcis, 02/25/2020 1

ASIC and FPGA

asic, die

Razavi RF Microelectrnonics

tarun.garg15, 02/24/2020 2

Research and Design

How to Debug Issue Due to Glitchy Clock V

Lyndsy, 02/24/2020 0

ASIC and FPGA

clock, glitch

HW Mailbox for On-Chip and Off-Chip Inter-Processor Communication V

Bill-Ramsey, 02/24/2020 1

ASIC and FPGA

fifo, mailbox

Case Study: How Memory Consumes High Leakage in Sleep Mode P

Precise-Design, 02/23/2020 0

ASIC and FPGA

low power, memory, power

Practical Consideration of Adaptive Voltage Scaling (AVS) V

vlsisuh, 02/20/2020 0

ASIC and FPGA

avs, power

Debug Memory Read Issue with Timing Analysis and Experiment V

Pendra, 02/15/2020 0

ASIC and FPGA

memory, timing

Verification of an Asynchronous Interface Design

Trydeman, 02/14/2020 0

ASIC and FPGA

asynchronous, verification

UVM for RTL Designers How to Drive Stimulus

dcimple, 02/14/2020 2

ASIC and FPGA

UVM, verification

Microcontroller Code Execution and ISP of Flash ROM and RAM

FRANH, 02/10/2020 0

ASIC and FPGA, Embedded and Firmware, MCU and DSP

bootloader, Flash, memory, microcontroller

DFT JTAG and ARM JTAG Security S
SD-RTL-DGN 03/15/2020

This is post #4 of 4 in the series “ARM and DFT JTAG” ARM and DFT JTAG discussion DFT...
Cadence HLS Stratus IDE Basic: How to Use the Example FIR Project
BrandonG 03/11/2020

This is post #1 of 3 in the series “Cadence HLS Stratus” Cadence HLS Stratus High level synthesis (HLS)...
DFT Scan Shift Current for IR Drop Analysis
Angpol 03/14/2020

When we do IR drop analysis, we would like to use the worst case current. The next question is...
OWE (Overall Wafer Effectiveness) and MFU (Mask Field Utilization)
QYang 03/17/2020

OWE (Overall Wafer Effectiveness) and MFU (Mask Field Utilization) are two closely related terms and both are about how...
ASIC RC Corners or Parasitic Interconnect Corners
KevinP1 03/19/2020

For ASIC timing closure lots of us know we need to check PVT corner. In deep submicron technology node,...
Cadence HLS Stratus: Analysis of FIR Example Project V
BrandonG 03/12/2020

This is post #2 of 3 in the series “Cadence HLS Stratus” Cadence HLS Stratus This post will take...
TrustZone, MultiZone, Security Check and Code Signing
Egeberg 03/15/2020

MultiZone security proposed by Hex Five for RISC-V is compared with ARM’s trustZone in my other post, Hex Five’s...
Transfer of High Rate Data With Source Synchronous and Other Methods S
SD-RTL-DGN 03/23/2020

This is post #5 of 5 in the series “Clock and Synchronization” Clock and synchronization First, there are two...
Some Considerations of ASIC Clock CTS and STA
KevinP1 03/22/2020

Let’s say a design has three clocks, clk1, clk2, and clk3. They are synchronous to each other. The Blog...
Cadence HLS Stratus: ecoFlow
BrandonG 03/17/2020

This is post #3 of 3 in the series “Cadence HLS Stratus” Cadence HLS Stratus Cadence Stratus IDE comes...

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