Does it matter if async reset deassert edge is not synced and Should we check async reset timing in timed GLS
This post is triggered by Ravenhill’s question Does it really matter if async reset’s deasset edge is not synced?...
ASIC Memory Low Power: Single Rail, Split Rail, and Low Power Modes
This is post #1 of 2 in the series “ASIC Memory Low Power” ASIC Memory Low Power Memory power...
SoC IO Pad, Bump, Ball, and Pin
It could be confusing to beginners what are ball, bump, pad, and pin in chip design. Hope this doc...
Use VCLP and UPF to report power domain crossing signals
In vclp shell, run below command report_crossover and it will report...
Crystal safety margin test and crystal startup time reduction
There are two common issues with usage of crystal. Crystal oscillation becomes unstable with the aging of crystal or...
Memory Function Path ATE Testing
Wayland Chen 12/08/2019
Memory BIST is well known and widely used to test on-chip memories. However, Mbist does not use function path....
Case study: how DFT output dedicated isolation cell causes issue in Burn-In test
This is post #3 of 3 in the series “some DFT topics” some DFT topics Recently our chip burn-in...
Transmission Gate Not to be Used on Voltage Domain Boundary
My other post, Transmission Gate and the Sneaky Leakage Path, discusses transmission gate should not used at power...
Verilog Initial Block Retriggering at Power up for RTL UPF Simulation
Initial block is widely used in verilog modeling. Here is its basic syntax. module macroA_behave reg valid_input; initial...
ASIC Memory Low Power: Memory Standby Mode and Memory Clock Gating
This is post #2 of 2 in the series “ASIC Memory Low Power” ASIC Memory Low Power UMC 40nm...