Single sided and double sided two way ranging formula and error
IEEE P802.15 Wireless Personal Area Networks has discussion about single-sided and double-sided two-way ranging. Some derivations are given at...
Verification of an Asynchronous Interface Design
Timing issue is one of hard to root cause bugs in chip design. You may have this kind of...
Microcontroller Code Execution and ISP of Flash ROM and RAM
Microcontrollers such as TI MSP430 series and Atmel AVR series are widely used in embedded systems. Microcontroller needs non-volatile...
Memory Function Path ATE Testing
Wayland Chen 12/08/2019 5 5/5 (1 )
Memory BIST is well known and widely used to test on-chip memories. However, Mbist does not use function path....
Practical Consideration of Adaptive Voltage Scaling (AVS)
There are lots of articles and discussions online about adaptive voltage scaling. But most of them just focus on...
Verilog Initial Block Retriggering at Power up for RTL UPF Simulation
Parker 12/08/2019 4.5 4.5/5 (2 )
Initial block is widely used in verilog modeling. Here is its basic syntax. module macroA_behave reg valid_input; initial...
Debug Memory Read Issue with Timing Analysis and Experiment
In lab we have an issue that on some parts and under certain condition, the content read out of...
Does it matter if async reset deassert edge is not synced and Should we check async reset timing in timed GLS
This post is triggered by Ravenhill’s question Does it really matter if async reset’s deasset edge is not synced?...
UVM for RTL Designers How to Drive Stimulus
UVM is widely used and beloved by design verification engineers. It is simple: work visibility and job security. In...
Crystal safety margin test and crystal startup time reduction
VinayClark 12/07/2019 5 5/5 (1 )
There are two common issues with usage of crystal. Crystal oscillation becomes unstable with the aging of crystal or...