Here are some questions I have for latch related design Why does clock gating ICG cell uses latch and...
Tag: timing
→ More TagsFor ASIC timing closure lots of us know we need to check PVT corner. In deep submicron technology node,...
In lab we have an issue that on some parts and under certain condition, the content read out of...
This is post #1 of 5 in the series “Clock and Synchronization” Clock and synchronization Here is our thinking...
One bigĀ problem between frondend team and backend team is miscommunication.Ā For example, to cut down power consumption, frondend teamĀ comes up...
Synapse has a good paper of primetime timing eco. Some key points are: In PrimeTime, there are two...
Above we have a clock mux. First we need to define clk1 and clk2. Assuming they are root/source clocks...
Cell characterization is a process of analyzing cell design, normally extracted as spice circuit, Ā to generate cell models...
Very good tutorial about within-die variation or otherwise called OCV (On-Chip Variation). A little bit. But fundamentals are not...
This is a study note. I have been working on gate level sim with some SDF timing issue these...
Find Zimmer Design Service. It has several very interesting ASIC Backend articles. Some were published on SNUG. List a...