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This is post #4 of 4 in the series “RHE Training” RHE Training Slides -sitesub_content-
Tag: Backend
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This is post #3 of 4 in the series “RHE Training” RHE Training Slides -sitesub_content-
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This is post #2 of 4 in the series “RHE Training” RHE Training Slides -sitesub_content-
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This is post #1 of 4 in the series “RHE Training” RHE Training Slides -sitesub_content-
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Let’s say a design has three clocks, clk1, clk2, and clk3. They are synchronous to each other. The Blog...
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For ASIC timing closure lots of us know we need to check PVT corner. In deep submicron technology node,...
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OWE (Overall Wafer Effectiveness) and MFU (Mask Field Utilization) are two closely related terms and both are about how...
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There are lots of online materials introducing Synopsys ptpx flow. This short article just captures the fundamental commands to...
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When backend closes timing, timing is checked at certain PVT corners which means out of this range it is...
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Cell characterization is a process of analyzing cell design, normally extracted as spice circuit, to generate cell models...
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A good tutorial about VLSI and backend process. vlsi-expert.com Some chapters: 10 Ways to fix setup and hold...
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Very good tutorial about within-die variation or otherwise called OCV (On-Chip Variation). A little bit. But fundamentals are not...
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Here we use a simple RTL design to go through the whole backend process, including synthesis, floorplan, placement, CTS,...
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Scripts: Overview Standard cell based IC design with hard macros such as analog PLL/ADC and memories (CPU is...
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This is post #1 of 3 in the series “some DFT topics” some DFT topics Here we use Synopsys...
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This is a study note. I have been working on gate level sim with some SDF timing issue these...
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Find Zimmer Design Service. It has several very interesting ASIC Backend articles. Some were published on SNUG. List a...
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Found this study note online. The format is messy. I think it is a mix of copy-and-paste with some...
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