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Digital IC Backend Lab showing the whole BE Process V

QYang, 03/07/2016 1

ASIC and FPGA, Education

Backend, cts, DFM, floorplan, route

Apply Cordic Algorithm to Digital FM Receiver V

JuanTang, 02/24/2016 1

Wireless

cordic, FM, receiver

5 5/5 (1 )

Employing Cordic Algorithm in Digital Wireless Receiver Design V

JuanTang, 02/24/2016 1

Wireless

cordic, DDS, receiver, rotation

5 5/5 (1 )

Specify ADC and AGC Requirements with ACI (Adjacent Channel Interference) V

JuanTang, 02/21/2016 0

Wireless

adc, agc, dynamic range

Dedicated ESD Supply and Ground Connection on Package V

MikeD, 02/20/2016 0

ASIC and FPGA, RF and Optics

esd

A Practical Design of Digital Fractional Sample Rate Conversion V

JuanTang, 02/17/2016 0

ASIC and FPGA

sample rate conversion

ASIC Power Switch Banks and Inrush Current Limit P

Precise-Design, 01/22/2016 2

ASIC and FPGA

inrush, power switch

5 5/5 (1 )

Basic Introduction of Modern SOC Reset Generation S

SD-RTL-DGN, 01/12/2016 1

ASIC and FPGA, PCB and Board Design

lvd, por, Real Time clock, reset, xtal

5 5/5 (1 )

Memory Based Programmable State Machine for Direct Hardware Control S

SD-RTL-DGN, 12/17/2015 1

ASIC and FPGA

FSM, programmable

5 5/5 (1 )

DFT Core Wrapper Cells from DFT Compiler and Logicvision V

AnkitKumar, 12/11/2015 0

ASIC and FPGA

Backend, dft

A Flexible Digital Fractional Clock Divider with Verilog Code P

JLarson, 12/10/2015 5

ASIC and FPGA

clock, clock divider, fractional

5 5/5 (2 )

Ground Connection and the Need for 2nd ESD Protection V

MikeD, 12/07/2015 0

ASIC and FPGA, RF and Optics

esd

Transmission Gate and the Sneaky Leakage Path P

JLarson, 12/07/2015 0

ASIC and FPGA

leakage, transmission gate

UPF Example and Using UPF in Real Silicon Design S

SD-RTL-DGN, 12/06/2015 1

ASIC and FPGA

low power, upf

5 5/5 (1 )

2×1 and Nx1 Glitch Free Clock Switching V

yRhoney, 12/04/2015 6

ASIC and FPGA

clock

5 5/5 (1 )

ARM JTAG and DFT JTAG as well as SWD and 1149.7 (Part II) S

SD-RTL-DGN, 10/29/2015 2

ASIC and FPGA

1149.7, DAP, JTAG, SWD

ARM JTAG and DFT JTAG as well as SWD and 1149.7 S

SD-RTL-DGN, 10/29/2015 0

ASIC and FPGA

1149.7, DAP, JTAG, SWD

Use DCM and MMCM for Xilinx FPGA Clock Deskew V

JingZh, 09/24/2015 5

ASIC and FPGA

clock, deskew, FPGA

4.7 4.7/5 (3 )

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