Study on Prototyping with Palladium and Synopsys HAPS-70

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Study on Prototyping with Palladium and Synopsys HAPS-70

For our project, we need to run prototyping of of a large system for three reasons:
1. Enable and speed up software development before silicon is back.
2. Test system with the real third-party devices.
3. Verification/simulation of RTL code. Our simulation env is UVM based and current bottleneck is long run time on Linux workstation. Hopefully the prototyping system can accommodate behavioral (non-synthesizable) verification code.

We first investigated a system called Palladium which is a hardware-assisted verification platform from Cadence and can dramatically reduce the verification run time compared to traditional workstation-based verification. With this speed-up, real software can also be tested on Palladium. User also has good visibility into the system for debugging purpose.

However, after some research we dropped this approach for two reasons. First, the cost of palladium is just too high. Second, compared to FPGA based system, palladium still suffers low performance which means our system could end up running at too low speed on Palladium.

Note Palladium do have two advantages over FPGA system. First, non-synthesizable verificaition code can be compiled and run on Palladium. You can think Palladium as just a workstation which happens to be optimized to speed up RTL verification. Second, RTL compile time for Palladium is much faster than that for an FPGA system since there is no such thing as timing closure on Palladium. Timing closure takes a big chunk of compile time for FPGA. This also makes Palladium more “stable” than FPGA since your code may not work on FPGA properly due to timing violations here and there.

Anyway, we dropped Palladium idea and look at FPGA based prototyping platform. There are quite a few on the market. What seems a good fit is Synopsys’ HAPs-70 platform.

HAPS-70 is a fully integrated solution with HAPS hardware and ProtoCompiler software. It claims fast time to results (about one week), 2-3x performance boost over traditional tools, and integrated simulator-like debug architecture providing good visibility into the prototype operation.


HAPS-70 is modular and scalable. It is based on Xilinx Virtex7 2000T devices, provides 4M to 288M ASIC gate capacity which is good enough for our system, and provides flexible interconnect technology. ProtoCompiler design flow is as below:


What is a common headache in prototyping a large system is design partition. In this case design is so big that it has to run on multiple FPGAs so how to partition design becomes critical. It is based on several factors such size of design blocks, intercommunication among design blocks, etc. A lot of times manual partition is done. Good about HAPS system is it provides ProtoCompiler partition engine which analyzes design and optimizes partition to minimize error and speed up iteration. It is flexible and constraint controlled, manual or hybrid.


A slides presented by Andy Jolley on SNUG 2014 outlines an interesting HAPS case study.

It shows you can lock design cores to particular Virtex7 FPGAs with instructions like:
assign_cell {Shader Core 1} {mb_1.uA}
bin_attribute -locked mb_1.uA
assign_cell {Shader Core 2} {mb_1.uB}
bin_attribute -locked mb_1.uB

Then define your HAPS-70 system capacity using:
board_system_create -haps -name haps70s72
board_system_create -add HAPS70_S48 -name mb_1
board_system_create -add HAPS70_S24 -name mb_2

Limit the utilization of each of the FPGAs:
# Use 80% of the available resources for all bins
bin_utilization -all_bins –resource_ratio {All 0.8 }

Select a simple pin multiplexing strategy:
# ACPM with NO Minimum and Maximum TDM rations
tdm_control –type ACPM


Then provide FPGA-FPGA channels/links:


Run ProtoCompiler and it shows issue pretty quick that multiplexing ratio is 12/13 and 16 which is too high:


Fix the ACPM ratio by limiting it to 12:
tdm_control -type ACPM -max_ratio 12

Rerun ProtoCompiler to generate FPGA BIN file.

Senior Engineer
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1 Comment
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    mutasem 4 years ago

    thank alot


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