This is a study note. I have been working on gate level sim with some SDF timing issue these days. Realized that as a frontend engineer, I lack some good understanding of Synopsys cell timing model. For example, how the delay is calculated, how to calculate cell delay, how to get connection/wire delay, what is propagation delay, what is transition delay, etc.
Found several good documents online. First one is http://my.ece.msstate.edu/faculty/reese/EE8273/lectures/synopsys/synopsys.pdf. Some important pages are shown below:
1. Synopsys uses multi-dimensional lookup table to specify cell delay.
2. One axis must be input transition time and the 2nd axis can be for example output net total capacitance load.
3. The “single” delay includes both propagation delay and transition delay.
4. Output transition time is also specified using lookup table.
All good. But what is propagation delay and transition delay and how they are defined? Searched web again. This time found an excellent thesis from Jos Budi Sulistyo. The thesis is titled “On the Characterization of Library Cells” from Virginia Polytechnic Institute. This 140+ page thesis has a very good analysis of library cell characterization. It covers concept, modeling, setup, and measurement of both timing and power characterization. Going back to our timing questions, the following several pages extracted from thesis clarify them perfectly.
So simply speaking, intrinsic delay is about cell itself, transition delay is due to load cap on output net, and slope delay is due to input signal slope (or transition). Seems all the delays are checked at 50% crossing level.
Full version of the thesis can be found here: http://scholar.lib.vt.edu/theses/available/etd-08302000-21580051/unrestricted/thesis.pdf