Most SoC designers may not hear of split-nwell cell and merged-nwell cell. Understandable. These cells are related to backend low power process and sort of transparent to frontend team in lots of cases. They affect power floorplanning and routing. If not properly planned, backend or power layout team may come back to ask to reassign the module into certain power domain, or group several modules into one module to ease power connection, reduce area, improve SoC Quality. Understanding of what these cells are about can then play a critical role in a successful low power SoC design.
But before we dive into split and merged nwell cells, let’s have a short review of the basic concepts and what is the issue which calls for these cells.
Taking an inverter as an example, the left side is the schematic view. It has a PMOS and a NMOS. Nwell is normally not shown in schematic view. The right side is the layout view. It shows PMOS has the nwell, PMOS’ drain is connected to VDD at the top bar which is the so-called VDD rail, and NMOS’ is connected to GND at the bottom bar which is the so-called ground rail.
Here is another view. Again, nwell is for PMOS. It also indicates PMOS’ nwell needs to be connected to high voltage (not ground) through PMOS’ B pin. But in most low power SoC layout, this is not how it is done. Will explain later.
Standard cell based SoC layout is area efficient. Cells are placed side by side in a row and there are multiple rows. In a row, cells share the same VDD rail and VSS rail. Adjacent two rows can share VDD rail or VSS rail. Normally a cell stays in one row and this kind of cell is called single-height cell. Some cells can occupy multiple rows. “Sleep transistor” in below diagram sits on two rows so this cell is also known as double-height cell.
Here is another view. Most cells are of single height but they have different widths. Obviously more complicated cells like a flip-flop uses more area/width than a simple cell like a inverter.
Let’s say we connect PMOS’ nwell to the same VDD rail. It works. But here is a typical issue in low power design. CPU sends a signal to module 2 and this signal is routed through module 1. Module 1 is in VDDX domain which means the VDD rail is connected to VDDX and nwell is also connected to VDDX. But we want the buffer on signal 1 to be powered by VDD_EXT which means when VDDX is turned off, since VDD_EXT is still on, the signal can properly go through. But how do we connect this buffer’s VDD and nwell? This is where AON (always on) buffer and split-nwell/merged-nwell cells kick in.
There are other scenarios like isolation cell, level shifter cell, etc., which also call for this kind of special cells.
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