Sort out Max/Min delay and derating factor confusions for single OC, best case worst case OC, and OCV

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Sort out Max/Min delay and derating factor confusions for single OC, best case worst case OC, and OCV

I’ve been working on ASIC frontend design for some time. Recently I am doing timing closure with backend folks. Got myself really confused about max/min delay and derating. What are and when to apply max/min delays? How to specify and when to use derating factors? I thought I already knew these. In addition, the more I google and read documents, the more I was confused since what I read seemed not consistent, …, until I sort it out.

For example, we have the following commands to set derating factors

set_timing_derate -max -early 0.8 -late 1.0
set_timing_derate -min -early 1.0 -late 1.1

Why do we need separate (early and late) derating for max and min? We do see below setting as well which doesn’t specify max or min.

set_timing_derate -early 0.95
set_timing_derate -late 1.05

So is it necessary to separate derating factors for max and min? BTW, if you don’t know, derating factor modifies cell/net delays in timing analysis and the follow equation holds

derated_delay= delay + (derating-factor – 1.0) * delay
Another example. We have the following diagrams

bcwc-setup

and

bcwc-hold

for setup and hold timing analysis.

Well, it doesn’t look right, right? We all know for setup check, the worst scenario is launching path has the longest delay and capturing path has the shortest delay. Therefore we should use max delays for launching path and MIN delays for capturing path. The diagram uses MAX delays for capturing path so the setup analyzed is not the worst case?
If you are confused as me, good news is I think I get it sorted out. Out of information online I googled, a big help comes from this slides:

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4 Comments
  1. mazhar 3 months ago
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    Really interesting blog. Thanks for sharing.

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    mutasem 4 years ago
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    thank you

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  3. Sarkar 5 years ago
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    Interesting blog. One comment is when PVT and RC corners are fixed, minimum and maximum delay not only comes from multiple paths but also from rise and fall time. vlsi-expert.com blog site has a good introduction about this part.

    4

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