When we talk about MCU chip reset, we have software reset and hardware reset. Software reset can be watchdog reset, NMI reset, bus fault reset, and so on so software can self detect issue and reset part or all of the logics inside MCU chip. Hardware reset can be implemented as a reset pin so user can toggle this pin to reset the chip for debugging purpose or upstream processor can toggle this pin to put the chip into reset state in certain scenarios. For example the chip may malfunction and doesn’t respond to upstream processor’s command.
Above resets is more on digital side. What is missing is two “analog” resets for a MCU chip to work properly, POR (power on reset) and LVD (low voltage detect) reset. As name suggests, when power is first applied to a MCU chip, POR reset needs to be properly applied. Here we use Atmel 80C51 app note
as an example to illustrate how POR works.
Above figure shows VDD and Xtal oscillator waveform for a properly started MCU. Two important parameters are t_osc and t_vddrise defined as:
T_osc: time needed by xtal oscillator to reach Vih1 or Vil1 level
T_vddrise: rise time of the power supply taken between 10% to 90% of VDD
So POR reset needs to be asserted and released to make sure
- Power supply of MCU chip reaches certain level and stays stable
- Xtal oscillates properly and the output clock frequency is stable. The following fig shows a good reset that fulfills these two needs.
On the other hand Fig3 and Fig4 show two improper cases. In the first case reset is applied during the window that Xtal is not started so MCU doesn’t get reset since there is no clock yet. Here looks Atmel 80C51 uses synchronous reset so clock is needed for reset to take effect. This may not be the case for other chips. In the second case reset is released before VDD reaches certain level and is stable. Therefore MCU chip supply voltage is too low which prevents the chip functioning properly.
Low voltage reset (LVD) happens similar to above 2nd case that when MCU chip supply voltage drops to certain level reset needs to be applied to chip to prevent malfunctioning MCU for damaging itself and other chips on board. This is simply because MCU internal logic is designed with a working voltage range and beyond that timing could be wrong and logic could behave abnormally. The following figure shows the reset behavior relative to VDD voltage and introduces POR or LVD.
To fulfill above needs for POR and LVD resets, external reset generation chip can be used. Here we use On-Semi MC34064 as an example.
Above figure shows block diagram of MC34064 internal logic and below fig shows reset output voltage versus input supply voltage. So MC34064 holds reset output low if power supply VDD is below certain level and leaves reset output open (high-Z) if power supply VDD is beyond the threshold.
Above figure shows the usage of this chip to reset a MCU chip. Here a capacitor called C_DLY is used to introduce reset delay relative to input VDD jump. Delay calculation is straightforward and shown in the figure. User can change C_DLY value to make sure t_DLY is large enough to make sure MCU VDD is stable and xtal osc output is also stable. Note this delay is only applied to the release of reset and not to the assertion of reset. In other words, let’s say VDD voltage drops as in LVD case. MC34064 detects low voltage and drives reset output low immediately which puts MCU chip into reset state without delay. When VDD voltage rises back, reset delay is introduced so reset is only released when certain time is passed.