Some Clarification of Max/Min Delays in STA and Timing Simulation

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Some Clarification of Max/Min Delays in STA and Timing Simulation

Here is our thinking about below questions:


What min/max delay mean? Is it due to worst/best operating condition?

We see STA report uses min/max delays but with derating applied. Then why derating is applied on top of min/max delays? In other words, max delay is not absolute max delay. With derating applied, it can be even larger? What then derating is really about?

SDF files can be max sdf, typical sdf, and min sdf. Why inside each sdf file there is still a (min, typ, max) triplet? Which element of this triplet is used by SDF timing simulation? Does SDF timing simulation check the scenario that STA closes timing?


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We are a small team of ASIC and FPGA design engineers with combined >40 years of experience. We successfully led several chips through the whole design to TO process. Familiar with Xilinx FPGA, we designed complicated system of using multiple FPGAs to verify complicated ASIC and also for the final products. We are interested in working as independent contractor for your projects. Feel free to contact us.


1 Comment
  1. rowe 2 months ago

    Nice presentation


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