SoC IO Pad, Bump, Ball, and Pin

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SoC IO Pad, Bump, Ball, and Pin

It could be confusing to beginners what are ball, bump, pad, and pin in chip design. Hope this doc helps to clarify a little bit.

Below is flip-chip, ie, FCBGA, cross-section diagram. Die is connected to package through bumps which is also called RDL bumps. Package is connected PCB board through balls or package balls. Package is just like PCB board which has metal routing and uses different material such as substrate instead of FR4 for PCB.

 

Here is a closer look of bump, RDL, die metal layers and die baselayer. RDL is redistribution layer. It is one or two layers of metal and it is used to connect IO pad to bump. Pin or RDL pin is nothing but a small piece of metal on RDL layer. On one side RDL pin is connected to bump through RDL metal wires. On the other side RDL pin is connected to IO pads, which is called IO buffers in below diagram, through die metal layers.

Let’s take a look how RDL pins are connected to bumps on RDL. Here RDL is one layer of metal.

Below shows how RDL pins are connected to bumps on RDL with two layers of metal, layer 9 and 10.

 

There are many discussion of how to assign pin and bump to minimize cross routing. Below is an example. In most cases this is transparent to chip designers and is only relevant to package designers.

 

 

As can be seen, ball, package, bump, RDL, RDL pin, and die metal layers are all just some metal connection. There is no active circuit yet. Real circuit is the IO pads or IO buffers. IO pads really handles voltage level, current driving strength, in or out, ESD protection, etc. If you want, you can always connect a metal wire (an internal signal) to a bump to make it visible to outside world. But obviously it is not preferred. ESD through the bump can easily damage your chip. That bump has normally low voltage than standard IO voltage so you can’t drive it externally easily. Even you drive, there is multiple driver issue inside chip and so on.

Given said, it is allowed to connect internal supply net to bump for monitoring purpose and for in-lab override debugging. Connecting supply net to bump is quite normal to minimize IR drop.

 

In SoC design it is quite common several groups will work on the same chip together. End of day what each group delivers is an gds file covering baselayer and metal layers. As mentioned above, RDL layer sits on top of metal layers. Normally each IP group doesn’t need to include RDL layer in their delivery. There is a dedicated package team working on RDL layer and external package. Obviously IP group and package team need to talk to each other and IP group needs to be aware of bump locations and RDL routing since their metal layers, including pads routing and PG supplies, need to be connected to RDL and bump.

 

Now here is a practical question. Another IP group says they are running out of space on their side and asks you if good to put a bump on top of your IP. How do you evaluate? Check if putting a bump on your IP top can cause area issue and routing congestion issue. If they will route signal on RDL layer from their IP to your IP, no need to change RTL to add pin for this new signal. Reason is RDL routing is not included in netlist since IP group doesn’t deliver RDL. If they want to route signal to your IP through metal layer and then inside your IP to RDL. You need to change RTL and netlist to add a pin.

 

 

 
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