On chip embedded memory is a critical building block of a System on Chip (SoC). It not only occupies a big chunk of chip footprint but also has a big impact on chip dynamic current and sleep current. Here memory refers to on chip static ram (SRAM).
There are several techniques to reduce the dynamic current of SRAM.
First, reduce usage of SRAM and use ROM as much as possible.
ROM is not only smaller than SRAM of the same size but also consumes less power. ROM is read only. How can we replace SRAM with read only ROM? A lot of times RAM holds instruction code and not data. Instruction code is read only once it is downloaded at SoC boot. Benefit of using RAM to hold instruction is flexibility. Code can be changed after chip is build. But if instruction, even part of it, is stable, placing it in ROM can reduce chip area and active current. ROM code can be patched if mistaken is found after chip is build.
Second, pay special attention to SRAM selection.
SRAM normally comes with different flavors such as size, aspect radio, etc. There is normally a trade off among area, speed, dynamic and leakage power. Simply put, to support higher read and write speed, memory area is larger, dynamic power per Mhz is higher, and leakage tends to be higher too. Select the most fit memory is an important step to reduce memory power.
What is worth mentioning is in deep sub micron era, standard cell can normally work at lower voltage than memory array. SRAM normally comes with split rail option. Split rail refers to memory array and memory peripheral have different supply rails. Memory peripheral is built on top of stand cells so with a dedicated supply rail it can work at lower voltage than memory array and therefore reduce dynamic current consumed by mem peripheral.
Third, related to SRAM selection, enable SRAM low power feature as much as possible.
If SRAM is not used and its content is not needed, power it down. If SRAM content is still needed, put SRAM into standby mode. What standby really means depends on SRAM implementation. It could mean shut down memory peripheral, or switch memory supply to some low voltage supply, etc. Standby can be statically entered and exited per control from firmware or hardware controller. To save more power, standby can be entered and exited per transaction. If there is no transaction put sram into standby and when transaction comes take sram out of standby. Check SRAM standby timing closely. In some SRAM design out of standby has timing penalty which slows down transaction.
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