Several Power related Design Issues

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Several Power related Design Issues

I would like to share several interesting power related “issues”. Start with several and will add more.


Does power off mean cell output is ‘x’?

If you run gate level simulation against a power aware netlist which is a netlist with power and ground connections, you will see when power is turned off, that power net becomes 0 and cell output becomes x. If you trace into cell’s verilog model, you will see the model normally checks power and ground inputs. If power input pin is 0 or ground input pin is 1, the model makes the cell output x.

But does it match real silicon behavior?

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