Worked on a digital project recently with some board schematic and layout engineers. There are several digital components on board and pretty much each of them has internal switching regulators. (Some may even have multiple inside) Switching regulator requires capacitor and inductor which are normally not integrated inside chip and are external. This short blog captures the discussion about regulator external cap and ind layout as well as some other layout points.
Some of drawings are from “Portable power ESD and layout design considerations” of Dr. Qian from TI.
In my previous blog, I mentioned decoupling caps. They need to be placed close to power pins. Here we stress one more point how to connect them. As shown below, it is preferred not to run narrow trace to these caps. In addition, current may need to be estimated ahead and if it is high you may need to widen the trace/pad and increase number of vias.
On our board, we have multiple components sharing the same power source. Some components are analog and sensitive and some are digital or power circuit and noisy. In this case, it is preferred to run separate power connections. But what is commonly forgotten is ground. As shown below, power circuit current return path goes through analog circuit return path and therefore couples noise into analog circuit.
Solution is as below to separate both power and ground connections.
The same concept is illustrated in below as well. Return current of noisy circuit runs underneath sensitive circuit and can still corrupt their ground reference.
A solution is to remove the noisy circuit from the ground plane. For example, run a separate ground wire for the noisy circuit.
Now let’s take a look of switching regulator cap and inductor layout. Below is a typical regulator connection.
First power components should be placed close to each other to minimize size of current loop and therefore reduce EMI and decoupling noise into surrounding circuits.
If power components are placed on both sides of board, concern is internal layer traces can be coupled with noise due to the noisy power current loop.
A better way may be to place power components on one side and use ground plane reduce inductive and capacitive coupling.
1. Keep power components, decouple cap and regulator cap/ind, close to IC with low inductance traces.
2. Use single point grounding.
3. Isolate analog signal paths from noisy power and digital paths.
4. Avoid vias when possible. Vias have high inductance and resistance which is especially worse for power traces. If necessary try to use multiple vias.
5. Pay special attention to high dv/dt or high di/dt signals. Run isolation if necessary.
6. Better to rout or pour ground planes manually as layout tool auto-router may screw things up here.
Last point. Layout is both science and art and it does make a difference. The following shows a poor layout can dramatically worsen the performance.