Most DFT related changes are not done in RTL phase. In other words, most DFT logics are not in rtl source code. A typical backend flow is after RTL is synthesized into netlist, DFT tool will read in this netlist and insert DFT logics such as LBIST and mBIST controllers, swapping regular FF with DFT FF and stitch DFT FFs together with scan chain. As a result, a typical design with DFT logics inserted look as below. This is extracted from online Logic Vision ScanBurst doc.
However, some DFT changes need to be done at RTL level. For example, clk and reset DFT changes, input/output pad handling, on-chip memory handling, scan chain related rtl change, and pwr domain consideration for DFT. So if you are new to a ASIC project, you may be wondering what are those RTL coding related to DFT. Hopefully this post can help answer these questions.
First, let’s take a look of DFT clk handling in RTL.
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