I am working on a task to generate true random number on an FPGA. True random number is not like pseudo-random number which can be generated using LFSR. The latter is well covered in text book. Googled and seems ring oscillator (RO) based true random number generator (TRNG) has gained lots of interests in both academic and application fields.

Math part is skipped here. Just look at how it is implemented. The following is a simple implementation. It shows how it works. One clock is used to sample another clock and at the sampling edge the other clock also toggles. It causes the well-known metastability issue that D input doesn’t satisfy setup/hold requirement of the D flipflop. Output is unknown. This unknown output is the random number we want.

The following is another implementation. Sampling clock needs to be picked so that it samples on D pin toggling edge. Note it introduces a LFSR to further whiten the random bit stream.

Here we give ring oscillator frequency formula. It is useful for ASIC based RO. For FPGA we can pick the gate cells and wire RO output to outside of FPGA and measure.

 

There are other implementations. All is based on the idea of metastable sampling.

 

Coherent sampling RO based TRNG

Multi-Ring Oscillator based TRNG

Transition effect RO based TRNG

Coherent Sampling based TRNG using PLLs

and self timed RO based TRNG

For details there is a good survey about above FPGA friendly RO-TRNGs authored by Oto Petura, etc.

 

Related there is an interesting paper in ISSCC 2018, an enhanced-security buck DC-DC converter with true-random-number-based pseudo hysteresis controller for internet-of-everything (IoE) devices. It uses below architecture to improve TRNG immunity to power injection attack.