Let’s say we have a simple design as below. There are two function modes. In one func mode, clk1 drives both block A and B and there are interconnects between A and B. In the other func mode, clk2 drives block B only and block A is not clocked and is not in use. In this article we will discuss how this design is tested in DFT mode. Or what clock rate should be used to test block A and B?
The following is author subscription content.
To gain access you can subscribe to this author's posts at Subscription of SD-RTL-DGN Posts. Subscription is valid for three months.
To gain access you can subscribe to this author's posts at Subscription of SD-RTL-DGN Posts. Subscription is valid for three months.
Highlights: 737 words, 6 images
Groups:
Tags:
