PTPX Peak Power

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PTPX Peak Power

There is a good question online about ptpx peak power. With

set_power_analysis_options -waveform_interval 0.1

(100ps interval) peak power is 2.2w. With

set_power_analysis_options -waveform_interval 0.01

(10ps interval) peak power jumps to 3.2w.


Here is the script to run ptpx:

set power_enable_analysis TRUE
set power_analysis_mode time_based
set link_library
" * DBH_1830BD18BA_GESVT1P8V_ISO_TT_1P8V_25C.db DBH_1830BD18BA_BD18LVGPIO_ISO_INLINE_TT_5P0V_25C.db b2hd111am4bi_8192x8x16_TT_25_1.80_TYP.db db2hd111am4bi_256x8x16_TT_25_1.80_TYP.db db2vs110am4bi_512x8x32_TT_25_1.80_TYP.db kpds18bcd64_r08w01_300c3pl_1v0_typ_1_1_172.db"
read_verilog ../tmax/test_top_1222_s.v
current_design test_top
read_sdc ./MCU.sdc
read_parasitics ../sim_post/test_top_1222_tt.spef
read_vcd -strip_path test_top_test/dut ../tmax/test_top_1225_p.vcd
set_power_analysis_options -waveform_format fsdb -waveform_output mac.fsdb  -include all_with_leaf -sdpd_tracking enabled 
report_power -verbose

Here is ptpx result:

Report : Time Based Power

Design : test_top
Version: K-2015.06
Date   : Fri Dec 29 09:28:08 2017

Sampling Interval: 0.001 ns

Library(s) Used:

    DBH_1830BD18BA_GESVT1P8V_ISO_TT_1P8V_25C (File: /home/worklib/DBH_STD_1830BD18BA_GESVT1P8V_ISO_16Q3_V2.20.10/LIBERTY/DBH_1830BD18BA_GESVT1P8V_ISO_TT_1P8V_25C.db)
    DBH_1830BD18BA_BD18LVGPIO_ISO_INLINE_TT_5P0V_25C (File: /home/worklib/DBH_IO_1830BD18BA_BD18LVGPIO_ISO_16Q4_V2.21.10/LIBERTY/DBH_1830BD18BA_BD18LVGPIO_ISO_INLINE_TT_5P0V_25C.db)
    b2hd111am4bi_8192x8x16_TT_25_1.80_TYP (File: /home/worklib/b2hd111am4bi_8192x8x16/lib/b2hd111am4bi_8192x8x16_TT_25_1.80_TYP.db)
    db2hd111am4bi_256x8x16_TT_25_1.80_TYP (File: /home/worklib/db2hd111am4bi_256x8x16/lib/db2hd111am4bi_256x8x16_TT_25_1.80_TYP.db)
    db2vs110am4bi_512x8x32_TT_25_1.80_TYP (File: /home/worklib/db2vs110am4bi_512x8x32/lib/db2vs110am4bi_512x8x32_TT_25_1.80_TYP.db)
    typ (File: /home/worklib/KPDS18BCD64-R08W01-300C3PL-1V0_031617_4977/KPDS18BCD64-R08W01-300C3PL-1V0_031617_4977/models/kpds18bcd64_r08w01_300c3pl_1v0_typ_1_1_172.db)

Operating Conditions: TT25   Library: DBH_1830BD18BA_GESVT1P8V_ISO_TT_1P8V_25C
Wire Load Model Mode: top

<no wire load model is set>

Power-specific unit information :
    Voltage Units = 1 V
    Capacitance Units = 1 pf
    Time Units = 1 ns
    Dynamic Power Units = 1 W
    Leakage Power Units = 1 W

      i  -  Including register clock pin internal power
      u  -  User defined power group

                        Internal  Switching  Leakage    Total
Power Group             Power     Power      Power      Power   (     %)  Attrs
clock_network           9.546e-04 2.653e-04 5.850e-08 1.220e-03 (19.10%)  i
register                1.118e-03 3.168e-04 6.348e-07 1.435e-03 (22.47%)  
combinational           7.329e-04 6.901e-04 4.905e-07 1.423e-03 (22.28%)  
sequential                 0.0000    0.0000    0.0000    0.0000 ( 0.00%)  
memory                     0.0000    0.0000    0.0000    0.0000 ( 0.00%)  
io_pad                     0.0000    0.0000    0.0000    0.0000 ( 0.00%)  
black_box               2.283e-03 1.332e-05 1.308e-05 2.310e-03 (36.16%)  

  Net Switching Power  = 1.285e-03   (20.12%)
  Cell Internal Power  = 5.089e-03   (79.66%)
  Cell Leakage Power   = 1.426e-05   ( 0.22%)
Total Power            = 6.388e-03  (100.00%)

X Transition Power     = 3.776e-05
Glitching Power        = 2.273e-08

Peak Power             =    3.2201
Peak Time              = 100247.114


It should be expected that lots of times with smaller interval peak power is higher. Indeed peak power is the average power across analysis interval. So with larger interval, peak power is averaged out over a longer period.

I saw this in lab measurement too. We use current meter to check current profile. Peak power will be higher if we set interval to be smaller. Same reason: peak power is the average power in interval.

But is it a real issue? It depends your chip’s decoupling cap design. Although peak power is high, it only last for a very short period of time. So many times on-chip caps can provide that peak current. Obviously out-of-chip decoupling cap is needed for current lasting a long time.


Senior Engineer
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1 Comment
  1. In the report, clock network consumes 19% pwr. Is it typical or a little bit high?


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