When backend closes timing, timing is checked at certain PVT corners which means out of this range it is not guaranteed to meet circuit operating condition. However, when circuit operates, it draws a large amount of current. No power distribution network is ideal and it introduces a small amount of resistance. Therefore when load current flows across power mesh network, there is IR drop introduced and as a result the voltage seen by gate cells will be reduced. This could cause circuit fail. IR analysis is to make sure the voltage droop introduced by IR drop is not big enough to cause circuit failure.
There are many documents online talking about IR drop. Here a Pspice model is built to show what voltages and currents look like during IR drop, how on-die capacitance is critical to combat IR drop, etc.
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