# Power Distribution on ASIC, Package, and PCB

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# Power Distribution on ASIC, Package, and PCB

External supply power is not connected to chip’s VDD and VSS directly. Connection goes through supply wire, PCB, packaging, and on-chip distribution network. Due to their inductance, power droop and ground bounce can be approximated as below:

$V_{DD} = V_{sup} -L_{VDDtotal}\frac{dI}{dt}$ ,

$VSS = L_{VSStotal}\frac{dI}{dt}$

There are several ways to reduce on-chip power distribution network inductance:

• make power grid more dense by reducing grid spacing and increasing grid width
• alternate power and ground planes so they are close to each other
• place power and ground pins close to each other

In addition, adding decoupling cap is a common way to reduce total power grid inductance.:

Decoupling caps can be put inside chip (Cchip), on package (Cpackage), and on board (Cpcb). Normally capacitor on PCB can be of large value but due to chip and packaging inductance, on-PCB capacitor is intended to provide low frequency current. On the other side, Cchip is inside ASIC so its value is limited but it has the least inductance to chip VDD. So Cchip is intended for high freq current. Cpackage is to provide medium freq current.

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