Photon Emission Microscopy (PEM) and optical beam induced current change (OBIRCH) are high efficient failure analysis techniques for fault localization on IC’s.
In principle PEM consists of a highly-sensitive CCD or InGaAs detector capable of detecting photons. These photons are emitted due to two mechanisms. First is due to recombination of electron-hole pairs when an electron-hole pair recombines in the active area (FEOL). Second is due to filed accelerated carrier radiation. For the first mechanism the wavelength of the light is about 1100 nm. It is 400nm to 1900nm for the 2nd mechanism. Both detectors have a typical wavelenght range but InGaAs has a better efficiency covering the complete range. Typical semiconductor related failures that can be covered by PEM are:
- Junction leakage
- Gate oxide defect
- ESD failures
- Latch Up
- Leakage currents
This diagram illustrates a typical PEM equipment setup.
Real PEM equipment setup from NanoPhysics.
For example, your chip has an extra leakage you can’t explain and you decide to use PEM to identify where the leakage happens on chip. First, you need to prepare a board with chip soldered on it. The board is better to be loosely populated without many components around your chip. This is for better accessability during PEM. The chip on board needs to be polished. Here are two ways. First, you can let PEM firm to polish chip first and then you solder it to board. Or you solder chip on board first and ask PEM firm to polish it. PEM firm may have preference one way or the other. It is IMPORTANT that if issue doesn’t show up on all chips, a setup with good chip should also be presented to PEM test. This is to compare the FEM imaging difference. Nevertheless there could be multiple bright spots identified by FEM. Some may be expected and some are not.
Next you need to prepare a detailed document how to setup the test so you can put your chip under the test condition. You may want to install a laptop with all the necessary tools. PEM firm likely has basic lab instrument such as power supplies but it is common you may need to bring some special equipment.
At last in PEM lab you test the setup first and double check the issue such as extra leakage can be duplicated. Then conduct PEM check. Through collection, enhance, photoelectric conversion and image processing by CCD to these photons, a Luminescent image is obtained. Overlay this image and the optical reflection on the surface of the device, failure localization can be made.
Here is a typical PEM image presented from “PEMIOBIRCH in Failure Localization of Flip-chip” presented at 2016 17th International Conference on Electronic Packaging Technology. As can be seen, a bright spot show up. Next is cross-check layout to find out what is over there and how it can cause issue. It is possible you have to grand DUT layer by layer to see what is the issue.
Photon Emission is complementary to OBIRCH but is more related to FEOL issues, where OBIRCH is suitable for FEOL as well as BEOL defects. There are many defects which don’t radiate photon (such as short circuit caused by metal interconnection melting). In these cases, optical beam induced current change plays an important role in failure localization. In Semiconductor materials, metal, polysilicon and doped silicon can absorb near infrared light and produce resistance change. For a semiconductor device applied with constant voltage, the current though it will change. Then the current change is recorded on a 2D image with value of each pixel representing the current change. Below diagram illustrate this process.
Then this 2D OBIRCH image is overlayed with device reflection image as in PEM to identify the bright spot which could indicate issue. Again, a comparison with good part image is very helpful to eliminate false alarm. Here is a typical OBIRCH image from “PEMIOBIRCH in Failure Localization of Flip-chip”.
Both PEM and OBIRCH can be performed either Frontside or Backside. A backside analysis is advised and has the advantage that no large metal tracks will block the emitted photons. Preparing a sample for Backside analysis requires more steps and special tools inlcuding skills. Frontside analysis suffice with a simple decapsulation or boil-out. Electrical connection can be made using dedicated test sockets or using probe needles.