PCIE Tutorial: PCIE Three Layers and Ack/Nak Protocol

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PCIE Tutorial: PCIE Three Layers and Ack/Nak Protocol


In this episode, we talk about PCIE protocol, three layers, packet type and assembly, and packet tx/rx as well as data link layer error detection and TLP Retry Buffer. It is a premium tutorial. Our first tutorial, PCIE enumeration, in series is a public post.

PCI/PCIE protocol defines three layers, transaction layer, data link layer, and physical layer. As shown below, data from software are first packaged in transport layer by appending TLP header and TLP ECRC. ECRC stands for end-to-end CRC and is 32 bits.


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We are a couple of RTL design engineers with combined more than 40 years of experience in ASIC and FPGA digital design. We successfully led several chips through the whole process from feature define, RTL design, verification, to backend/DFT support, TO, and bring-up. We are familiar with Xilinx FPGA design too and have experience in using multiple FPGAs to verify complicated ASIC RTL design or for the final product. We are interested in working as independent contractor for your projects. Please send us private message if there is a match. Thank you!

1 Comment
  1. orr101 2 years ago

    With all due respect, 15$ or 3 months of your content is WAAAY too much.


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