PCIE Tutorial: PCIE Error

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PCIE Tutorial: PCIE Error

In this episode we are going to touch PCIe error handling. First, two good references about this topic. The first is the well known “PCI Express System Architecture” from Mindshare. The second is a good article on Design and Reuse dedicated to this topic, PCIe Error Logging and Handling in a Typical SoC.

Different from above two articles, this article tries to introduce this topic from user point of view. This means we don’t dive into detail immediately. Instead, we tend to give a overall picture and only touch details whenever needed.

As explained later, there are many types of PCIe errors. But in general, PCIe error handling follows below flow. PCIe device can detect, log, and report PCIe errors to PCIe root complex. PCIe host software will then handle reported PCIe error when interrupted by PCIe root complex.

Below is the detailed flow chart for error logging and reporting on PCIe device side.

 

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We are a small team of ASIC and FPGA design engineers with combined >40 years of experience. We successfully led several chips through the whole design to TO process. Familiar with Xilinx FPGA, we designed complicated system of using multiple FPGAs to verify complicated ASIC and also for the final products. We are interested in working as independent contractor for your projects. Feel free to contact us.
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