PCIE Tutorial: Enumeration

Make it to the Right and Larger Audience

Blog/Press Release

PCIE Tutorial: Enumeration

Software reads bus 3 dev0 and figures it is a PCIE end point. So it goes back to update bus 2 dev0 sub bus number from 255 to 3. Then it checks if bus 2 has dev 1. Find it. Assign bus 4 and update bus 2 dev 1 sec bus num to 4 and sub bus num to 255.

pcie_enum5

 

Software reads bus 4 dev0 and figures it is a PCIE end point. So it goes back to update bus 2 dev1 sub bus number from 255 to 4. Then it checks if bus 2 has dev 2. Find it. Assign bus 5 and update bus 2 dev 2 sec bus num to 5 and sub bus num to 255. It then reads and figures bus 5 dev 0 is end point so it goes back to update bus 2 dev 2 sub bus num to 5.

pcie_enum6

Software further checks if bus 2 has dev 3. It goes ahead and read bus dev 3 configuration space. Since there is no dev 3, this transaction eventually times out causing a master abort inside RC and RC returns data of all one’s to software. So software knows no bus 2 dev 3. It then goes back to update bus 1 dev 0 sub bus number from 255 to 5 and further goes back to update bus 0 dev 0 func 0 sub bus number from 255 to 5.

pcie_enum7

 

Software already know bus 0 dev 0 is a multi-function device in step 1. So it moves to bus 0 dev0 func 1. Assign bus 6 to its downstream link. Reads bus 6 dev 0 and figures it is a end point. Eventually bus 0 dev0 func1 sec bus num is assigned to 6 and sub bus num also to 6.

pcie_enum8

 

Software checks and sees bus 0 dev 1. Assign bus 7 and update both sec bus number and sub bus number to be 7. Software further checks if there is bus 0 dev 2. No such device. Transaction times out. That’s it. Software gets the whole system figured out and properly configured. PCIE enumeration is done.

pcie_enum9

 
Profile Photo
We are a small team of ASIC and FPGA design engineers with combined >40 years of experience. We successfully led several chips through the whole design to TO process. Familiar with Xilinx FPGA, we designed complicated system of using multiple FPGAs to verify complicated ASIC and also for the final products. We are interested in working as independent contractor for your projects. Feel free to contact us.
10 Comments
  1. If the device on bus 5 is absent, scheme will be that, right?

    5
  2. alexsdsd69 3 months ago
    0
    -0

    nice

    0
  3. Gokul 3 months ago
    0
    -0

    What about hotplug devices ?
    is it possible to fix bus number of device to some fixed number based on device id ?

    0
  4. Saurabh 4 months ago
    0
    -0

    The configuration reads/writes which are done… is it done via CFG TLPs send via RC or some other mechanism??

    0
  5. sagarkumarbain 12 months ago
    +1
    +1 -0

    Good explanation for enumeration

    0
  6. AGHarish 1 year ago
    0
    -0

    The Best explanation for PCIe enumeration that I have read till date! Thank you very much for the article. Keep up the good work.

    0
  7. akhilreddy991 3 years ago
    0
    -0

    Awesome explanation

    5
  8. chandra_vs9 4 years ago
    0
    -0

    when two devices are there on same bus, say bus 1, how device number is decided ? when enumeration SW tries to read on B/F 1,0,0 which of these two devices responds ?

    0
    • xiaomi 4 months ago
      0
      -0

      PCIE link is end to end link, so it is impossible that more than one device link on one PCIE link. (what you called it bus)

      0
  9. maheswarudu 4 years ago
    0
    -0

    Nice explanation.

    0

Contact Us

Thanks for helping us better serve the community. You can make a suggestion, report a bug, a misconduct, or any other issue. We'll get back to you using your private message ASAP.

Sending

©2020  ValPont.com

Forgot your details?