PCIE Configuration Space and Example to Enable L1SS ASPM with Config Space Access

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PCIE Configuration Space and Example to Enable L1SS ASPM with Config Space Access

PCIe compatible devices have a set of status and control registers know as configuration space. PCIe host needs to be able to access these registers for proper operation of the devices. Below shows memory mapping of a typical PCIe device configuration space.

The first 64 bytes, with byte address from 0x0 to 0x3f, is PCI Configuration Header. There are two formats. One of the two formats is shown in the left side of below diagram and has pre-defined bit mapping. There are 16 DW (double word) in total which is 64 bytes. PCIe spec defines word as 8 bits and double world (DW) as 16 bits.

The next 192 bytes, with byte address from 0x40 to 0xff, is PCI compatible device specific configuration register space. There are multiple PCI capabilities. Each capability can have multiple registers. Each register can have multiple bytes. A PCIe device does not need to implement all the PCI capabilities and when it implements some capabilities, location of capability registers can vary. PCIe standard uses link list to access these capabilities. In PCI configuration header, the first byte of DW13 is the capability pointer which points to the 1st device specific capability. In below example, we use power management capability as the 1st device specific capability. The 1st DW of a capability is always capability header with bits [7:0] as capability ID (01 indicates it is PM capability and it is defined in PCIe spec) and bits [15:8] as pointer to next capability. With each capability, there is no need to use pointer because the format is pre-defined in PCIe spec. Taking PM capability as an example, the 1st DW is header as just mentioned, the 2nd DW is always PM capability register, and the 3rd and 4th DWs are always PM status and control register.


Note each pointer is 8 bits which can address 256 byte space which is exactly the combined space of PCI configuration header (64 bytes) and PCI device specific configuration space (192 bytes). This is also known as PCI configuration space.

PCIe extends configuration space to 4096 bytes with the first 256 bytes backward compatible as PCI configuration space. PCIe also defines multiple PCIe capabilities and it is up to device which capabilities to implement and where to put capability registers if implemented. But above PCI capability pointer is only 8 bits and how does it address 12 bit space (4096 bytes means 12 bit address)?

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We are a small team of ASIC and FPGA design engineers with combined >40 years of experience. We successfully led several chips through the whole design to TO process. Familiar with Xilinx FPGA, we designed complicated system of using multiple FPGAs to verify complicated ASIC and also for the final products. We are interested in working as independent contractor for your projects. Feel free to contact us.


  1. mengyao 9 months ago

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