A SPMI system supports up to 4 masters and 16 slaves. It is a low pin count, low speed bus originally intended to control power management chip but later find a much wider usage.
SPMI has two important concepts, BOM and RCS. Better to understand them well to understand who can initialize an SPMI transaction and who drives SCLK and SDATA two signals.
BOM stands for Bus Owner Master. SPMI supports up to 4 masters. Any of them can be a BOM and which master takes the BOM role dynamically changes. Only BOM drives SCLK. At any time only one BOM exists for a SPMI system.
RCS stands for request capable slave. SPMI supports up to 16 slaves. A slave can be either RCS or non-RCS. Only a master and RCS can initialize a SPMI transaction. So RCS feature allows a RCS slave to access other slave or master.
When SPMI bus is idle, there is a BOM driving SCLK low and monitors SDATA. If a master or a RCS would like to init a transaction, it drives SDATA high. When BOM sees SDATA high, it outputs two SCLK cycles. At the falling edge of the 1st SCLK cycle, the master or RCS releases (not drive) SDATA. At the rising edge of 2nd SCLK cycle, BOM drives SDATA low. This is shown in below diagram. Pay special attention to line pattern (solid or dotted) and line color to understand which device drives.
The third SCLK cycle is named “C” cycle. It is for a new master to connect to the system. But note both master address, MID or master ID, and slave address, USID or slave ID, can be statically assigned.
The 4th SCLK cycle is named “A” cycle. A is one way for a RCS to request a transaction. If A is driven 1 by a RCS as shown in Fig 21, bus enters A-type “Slave Arbitration” stage. Eventually one RCS will win the bus and that RCS will drive SDATA in the following command frame. Note during command frame stage, SCLK line is still in black color so SCLK is still driven by the BOM.
In Fig 22, A bit is 0 so RCS asserts A bit. Bus enters “Master Priority Arbitration” stage. This allows a master to request bus. Fig 22 shows the case that no master requests bus and then a RCS asserts SR=1 so bus enters SR-type “Slave Arbitration”. Similar to A-type “Slave Arbitration”, eventually one RCS will win the bus and that RCS will drive SDATA in the following command frame. If you would like to know how this slave arbitration is done, here it is:
“A Request Capable Slave device participating in the arbitration shall read SDATA on the falling edge of SCLK. If SDATA does not match the Slave Address bit SA value for the Slave device then the Slave device shall stop participating in the arbitration process and shall maintain its SDATA driver in a high-Z state for the remainder of the Slave Arbitration process. ”
The same process repeates for SA[2:0].
Below is flow chart of bus arbitration.
Master also has two arbitration, master priority arbitration in Fig 24 and master secondary arbitration in Fig 25. What needs to be pointed out is if a master wins the bus, it becomes BOM. During the following frame phase, this new BOM or the master requesting bus drives both SCLK and SDATA.
Hope you understand how SPMI bus arbitration works. Now let’s take a look of command and data frames.
When a master or a RCS wins bus, it drives a command frame on SDATA. Below are all SPMI commands supported.
Fig 52 is register write (0x40-0x5f). The whole command frame is 12bit. The upper 4 bits are normally SA[3:0] of slave address. The lower 8 bits is command frame payload. 0x40-0x5f is because for register write, the lower 5 bits specifies register address. Note register write/read command holds 5bit register addr.
Each register is always 8 bit. So for register write, data frame holds 8 bit data written into this slave register.
For register 0 write, there is a dedicated command. No need to specify register addr.
Fig 41 and Fig 42 show extended register write/read. Note the 1st data frame of extended register write/read command specifies 8bit register addr.
4bit BC[3:0] is byte count which specifies # of bytes or # of registers to be written or read since each SPMI register is 8 bits. Wit BC[3:0], extended register write/read command can access up to 15 registers. Register address, A[7:0], in the 1st data frame of the command is the starting register address for this multiple-reg transaction.
Fig 50 shows extended register write long command. Note the 1st and 2nd data frame of extended register write/read long command specifies 16bit register addr which can address much wider space.
You can think each slave register has a 16bit address so 64KB space. If not full 16bit address is provided by, ie, register write/read command or extended register write/read command, the upper missing address bits are padded with 0’s.
Below are master write/read command
Below shows SPMI commands for reset, sleep, shutdown, and wakeup.