show less
show more
Young Rhoney
4.5
-
2×1 and Nx1 Glitch Free Clock Switching
V
yRhoney 12/04/2015 5 5/5 (1 )
There was no activity posted yet.
yRhoney commented on the post, 2×1 and Nx1 Glitch Free Clock Switching 1 year, 1 month ago · , 0, 0
Point taken. This article extends eetimes article so i was taking a short cut
yRhoney commented on the post, 2×1 and Nx1 Glitch Free Clock Switching 1 year, 1 month ago · , 0, 0
Glad it helps.
yRhoney commented on the post, Two Potential Issues with Glitch Free Clock Muxing 1 year, 1 month ago · , 0, 0
I see what Trydeman means. Both issues are valid. Let me update my original post trying to address the 2nd issue and potentially the 1st issue too.
yRhoney replied to the topic Delta Delay in VHDL and Verilog in the forum
ASIC and FPGA 5 years, 1 month ago · , 0, 0
For Verilog, only non-blocking assignments cause delta delays. Blocking statements (no matter continuous or procedure assignments), do not cause delta delay. It is unlike in VHDL where all signal assignments cause delta delay.
Consider the following four models of clock buffers, only…[Read more]
yRhoney replied to the topic Delta Delay in VHDL and Verilog in the forum
ASIC and FPGA 5 years, 1 month ago · , 0, 0
For Verilog, only non-blocking assignments cause delta delays. Blocking statements (no matter continuous or procedure assignments), do not cause delta delay. It is unlike in VHDL where all signal assignments cause delta delay.
Consider the following four models of clock buffers, only…[Read more]
yRhoney replied to the topic Delta Delay in VHDL and Verilog in the forum
ASIC and FPGA 5 years, 1 month ago · , 0, 0
For Verilog, only non-blocking assignments cause delta delays. Blocking statements (no matter continuous or procedure assignments), do not cause delta delay. It is unlike in VHDL where all signal assignments causes delta delay.
Consider the following four models of clock buffers, only…[Read more]
yRhoney replied to the topic Delta Delay in VHDL and Verilog in the forum
ASIC and FPGA 5 years, 1 month ago · , 0, 0
For Verilog, only non-blocking assignments cause delta delays. Blocking statements (no matter continuous or procedure assignments), do not cause delta delay. It is unlike in VHDL where all signal assignments causes delta delay.
Consider the following four models of clock buffers, only…[Read more]
yRhoney replied to the topic Delta Delay in VHDL and Verilog in the forum
ASIC and FPGA 5 years, 1 month ago · , 0, 0
For Verilog, only non-blocking assignments cause delta delays. Blocking statements (no matter continuous or procedure assignments), do not cause delta delay. It is unlike in VHDL where all signal assignments causes delta delay.
Consider the following four models of clock buffers, only…[Read more]
yRhoney replied to the topic What tool do you guys use to draw digital circuit diagram? in the forum
ASIC and FPGA 5 years, 1 month ago · , 0, 0
You can take a look of my blog 2×1 and Nx1 Glitch Free Clock Switching. The digital circuits were drawn using Digikey Scheme-IT. It is online and free. Ok but can certainly be improved. For example, it doesn’t have D-FF with inverted clk in. Doesn’t allow you to draw a box to include other…[Read more]