Stan Hayward
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Design and Verification Slides and Papers from DVCon 2016 is Available
StanH 07/21/2016 -
[Slides] Clock and Data Recovery for Serial Digital Communication
StanH 12/07/2015 -
[Tool] Run RTL Design and TB Online with UVM OVM
StanH 01/06/2016 -
“PCIE Express System Architecture” from Mindshare
StanH 10/11/2015
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StanH commented on the post, PCIE Tutorial: Hardware Oriented ASPM Link State and L1 Substates 2 years, 1 month ago · , 0, 0
How to determine when to enter L1 from L0?
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StanH replied to the topic Large data to transfer from FPGA to FPGA do I need SDRAM to buffer data? in the forum
ASIC and FPGA 5 years, 2 months ago · , 0, 0
SDRAM is not that hard to work with. If you have limited knowledge about it or if it is your first time using it, you can always find some open source SDRAM controller IP as a reference. Also Xilinx and Altera both come with controller core.
As for external SRAM, their mem size is limited.…[Read more]
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StanH replied to the topic Large data to transfer from FPGA to FPGA do I need SDRAM to buffer data? in the forum
ASIC and FPGA 5 years, 2 months ago · , 0, 0
It depends. Data transfer rate can be very high since it is FPGA to FPGA and you can always use many data signals to achieve higher data rate. So likely you can dump data from one FPGA to the other without external buffer. (of course you need to consider data assemble and de-assemble…[Read more]
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StanH started the topic Your most weird board design issue in the forum
PCB and Board Design 5 years, 4 months ago · , 0, 0
Hi Guys
It is interesting to share our most weird board design issues.
StanH posted in
MCU and DSP 1 year, 6 months ago · , 0, 1
China’s chipmakers could use #RISC-V to reduce impact of US sanctions
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StanH posted in
MCU and DSP 2 years ago · , 0, 1
Microsemi releases #risc-v based low power fpga system for linuc plus real time app
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