RTL FE Design Team in SDB
We are a small team of ASIC and FPGA design engineers with combined >40 years of experience. We successfully led several chips through the whole design to TO process. Familiar with Xilinx FPGA, we designed complicated system of using multiple FPGAs to verify complicated ASIC and also for the final products.
We are interested in working as independent contractor for your projects. Feel free to contact us.
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DFT JTAG and ARM JTAG Security S
SD-RTL-DGN 03/15/2020 -
Clock Tree Balancing
SD-RTL-DGN 05/21/2019 5 5/5 (1 ) -
Quiz, How to Test This Simple Two Clock Structure S
SD-RTL-DGN 07/07/2019 -
PCIE Tutorial: PCIE Error S
SD-RTL-DGN 07/09/2019 -
Transfer of High Rate Data With Source Synchronous and Other Methods S
SD-RTL-DGN 03/23/2020
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Veteran ASIC/FPGA RTL Design Team
SD-RTL-DGN 02/01/2016$50
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Subscription of SD-RTL-DGN Posts
SD-RTL-DGN 01/14/2016$10
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Ltremblay posted on SD-RTL-DGN‘s wall 4 years, 9 months ago · , 2, 0
@sd-rtl-dgn More PCIe tutorial about retry, flow control, etc.?
Hello SD RTL, I really enjoy your PCIe tutorial series. It is a good supplement to the PCIe book from Mindshare. I’d like to learn some details about retry, flow control, low power, link training, etc. Do you plan to cover…[Read more]
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SD-RTL-DGN commented on the post, Verilog Initial Block Retriggering at Power up for RTL UPF Simulation 1 year ago · , 0, 0
Nice
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SD-RTL-DGN commented on the post, PCIE Tutorial: PCIE Three Layers and Ack/Nak Protocol 1 year, 4 months ago · , 0, 0
see above. Your order somehow was canceled and your payment was refunded
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SD-RTL-DGN commented on the post, PCIE Tutorial: PCIE Three Layers and Ack/Nak Protocol 1 year, 4 months ago · , 0, 0
Your order somehow was canceled. Your payment was refunded. We are checking with website why it is canceled.
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SD-RTL-DGN posted a new activity comment 1 year, 4 months ago · , 0, 0
Universal Verification Methodology (UVM)-Based Stream Generator Environment for RISC-V Cores
Contributed by Google, the environment provides configurable, highly stressful instruction sequences that can verify architectural and micro-architectural corner-cases of designs.SweRV…[Read more]
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SD-RTL-DGN replied to the topic Verilog test BFM to drive and monitor internal AHB bus in the forum
ASIC and FPGA 4 years, 4 months ago · , 0, 0
In Verilog, you can specify signal hierarchy path to drive or monitor DUT internal signals. For example:
interface dut_if(input bit clk); bit cntrl_enb; // from control logic [7:0] cntrl_data; // from control force top.dut1.data= cntrl_data; endinterface module dut(input bit clk);…
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SD-RTL-DGN replied to the topic Run multiple tests out of the same modelsim compiled work library? in the forum
ASIC and FPGA 4 years, 4 months ago · , 0, 0
What hollis mentioned is on the RTL side.In fact test cases tend to have their own test tasks, sequences, etc. The compiled library will be different even RTL is the same. So in regression tests, each test has their compiled library. Yes it is not optimal due to long compilation time. One…[Read more]
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SD-RTL-DGN commented on the post, Gate level SDF timing simulation does not simulate setup or hold scenarios seen by STA? 4 years, 6 months ago · , 1, 0
As for whether GLS is necessary, here is a blog from Gordon Allan.
https://blogs.mentor.com/verificationhorizons/blog/2015/02/26/is-gate-level-simulation-still-required-nowadays/Short answer is yes. Allan lists reasons like bad STA constraints, changes due to backend process, ECO,…[Read more]
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SD-RTL-DGN posted a new activity comment 4 years, 6 months ago · , 0, 0
Sure. We are working on it.
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SD-RTL-DGN posted a new activity comment 4 years, 9 months ago · , 0, 0
Thanks Ltremblay. It is in our plan to touch details of the topics you mentioned. Stay tuned.
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SD-RTL-DGN replied to the topic What tool do you guys use to draw digital circuit diagram? in the forum
ASIC and FPGA 5 years, 1 month ago · , 0, 0
MS powerpoint doesn’t have built-in electronics symbols. But if you google “electronics symbol for PPT”, you will some online resources for it. For example, the following two ppts have good electronics symbols which makes your drawing in PPT much…[Read more]
SD-RTL-DGN posted an update 1 year ago · , 0, 1
Remember you can synthesize a design with waveform to achieve low power
Synopsys has Power Compiler introduced for years. It takes in simulation waveform and synthesizes a design to achieve low power based on signal toggling information gathered from the waveform. You can specify multiple…[Read more]
SD-RTL-DGN posted in
ASIC and FPGA 1 year, 4 months ago · , 2, 1
CHIPS Alliance, an open source hardware association
Formed early this year, CHIPS (Common Hardware for Interfaces, Processors and Systems) Alliance harnesses the energy of open source collaboration to accelerate hardware development.
CHIPS Alliance aims to host implementation efforts…[Read more]
SD-RTL-DGN posted an update 2 years, 10 months ago · , 0, 0
Pcie pme#, wake#
When system puts device into d3hot, it is possible that device wakes up itself due to detecting some event and wants to talk to system. How does device wake up system in this case?
Device can use beacon or wake# to wake up system. Wake# is a just a hw wire. On device side…[Read more]
SD-RTL-DGN posted an update 2 years, 10 months ago · , 0, 0
Pcie bus master and msi
Bit2 of command reg in pcie config space specifies if device can initiate a pcie transaction or not. 1 means can.
Detail in https://wiki.osdev.org/PCI
In config space there is msi capability reg, msi address reg, and msi data reg. At enumeration, system software…[Read more]
SD-RTL-DGN posted an update 4 years, 5 months ago · , 0, 1
Good introduction about NVMe by Amber Huffman of Intel
http://www.flashmemorysummit.com/English/Collaterals/Proceedings/2016/20160809_FA11_Huffman.pdf
SD-RTL-DGN posted in
ASIC and FPGA 4 years, 6 months ago · , 2, 2
Igor Keller of Cadence warns non-Gaussian distributions below 16/14nm
which means OCV, AOCV, or even POCV and SOCV used in STA can be broken.
SD-RTL-DGN posted in
Networking and Interconnect 4 years, 6 months ago · , 0, 0
PCIe 4.0 heads to Fab and 5.0 to Lab
It’s been more than six years since the PCI SIG ratified its last major standard, the 8 GT/s PCIe 3.0. At the time it started the 4.0 version it thought it might be its last copper-based chip-to-chip interconnect. But since then Ethernet and Fiber C…[Read more]