show less
show more
RTL FE Design Team in SDB
65.0
-
Clock Tree Balancing
SD-RTL-DGN 05/21/2019 5 5/5 (1 ) -
Quiz, How to Test This Simple Two Clock Structure
S
SD-RTL-DGN 07/07/2019 -
DFT JTAG and ARM JTAG Security
S
SD-RTL-DGN 03/15/2020 -
Transfer of High Rate Data With Source Synchronous and Other Methods
S
SD-RTL-DGN 03/23/2020 -
PCIE Tutorial: PCIE Error
S
SD-RTL-DGN 07/09/2019
-
Veteran ASIC/FPGA RTL Design Team
SD-RTL-DGN 02/01/2016$50
-
Subscription of SD-RTL-DGN Posts
SD-RTL-DGN 01/14/2016
$10
SD-RTL-DGN posted an update 9 months, 4 weeks ago · , 0, 1
Remember you can synthesize a design with waveform to achieve low power
Synopsys has Power Compiler introduced for years. It takes in simulation waveform and synthesizes a design to achieve low power based on signal toggling information gathered from the waveform. You can specify multiple…[Read more]
SD-RTL-DGN posted in
ASIC and FPGA 1 year, 1 month ago · , 2, 1
CHIPS Alliance, an open source hardware association
Formed early this year, CHIPS (Common Hardware for Interfaces, Processors and Systems) Alliance harnesses the energy of open source collaboration to accelerate hardware development.
CHIPS Alliance aims to host implementation efforts…[Read more]
SD-RTL-DGN posted an update 2 years, 7 months ago · , 0, 0
Pcie pme#, wake#
When system puts device into d3hot, it is possible that device wakes up itself due to detecting some event and wants to talk to system. How does device wake up system in this case?
Device can use beacon or wake# to wake up system. Wake# is a just a hw wire. On device side…[Read more]
SD-RTL-DGN posted an update 2 years, 7 months ago · , 0, 0
Pcie bus master and msi
Bit2 of command reg in pcie config space specifies if device can initiate a pcie transaction or not. 1 means can.
Detail in https://wiki.osdev.org/PCI
In config space there is msi capability reg, msi address reg, and msi data reg. At enumeration, system software…[Read more]
SD-RTL-DGN posted an update 4 years, 2 months ago · , 0, 1
Good introduction about NVMe by Amber Huffman of Intel
http://www.flashmemorysummit.com/English/Collaterals/Proceedings/2016/20160809_FA11_Huffman.pdf
SD-RTL-DGN posted in
ASIC and FPGA 4 years, 3 months ago · , 2, 2
Igor Keller of Cadence warns non-Gaussian distributions below 16/14nm
which means OCV, AOCV, or even POCV and SOCV used in STA can be broken.
SD-RTL-DGN posted in
Networking and Interconnect 4 years, 3 months ago · , 0, 0
PCIe 4.0 heads to Fab and 5.0 to Lab
It’s been more than six years since the PCI SIG ratified its last major standard, the 8 GT/s PCIe 3.0. At the time it started the 4.0 version it thought it might be its last copper-based chip-to-chip interconnect. But since then Ethernet and Fiber C…[Read more]