SD-RTL-DGN

In Verilog, you can specify signal hierarchy path to drive or monitor DUT internal signals. For example:

interface dut_if(input bit clk);
bit cntrl_enb;       // from control
logic [7:0] cntrl_data; // from control

force top.dut1.data= cntrl_data;
endinterface

module dut(input bit clk);…

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What hollis mentioned is on the RTL side.In fact test cases tend to have their own test tasks, sequences, etc. The compiled library will be different even RTL is the same. So in regression tests, each test has their compiled library. Yes it is not optimal due to long compilation time. One…[Read more]

MS powerpoint doesn’t have built-in electronics symbols. But if you google “electronics symbol for PPT”, you will some online resources for it. For example, the following two ppts have good electronics symbols which makes your drawing in PPT much…[Read more]

Good question. Believe it or not, even in large companies, sometimes this issue pops up and not all engineers have a good handling of it. Yes, there is a better way to handle it. You should remove the delta delay due to gating logic. In this way, no matter how many layers of clock gating…[Read more]