We are a small team of ASIC and FPGA design engineers with combined >40 years of experience. We successfully led several chips through the whole design to TO process. Familiar with Xilinx FPGA, we designed complicated system of using multiple FPGAs to verify complicated ASIC and also for the final products.
We are interested in working as independent contractor for your projects. Feel free to contact us.
It’s been more than six years since the PCI SIG ratified its last major standard, the 8 GT/s PCIe 3.0. At the time it started the 4.0 version it thought it might be its last copper-based chip-to-chip interconnect. But since then Ethernet and Fiber C…[Read more]
@sd-rtl-dgn More PCIe tutorial about retry, flow control, etc.?
Hello SD RTL, I really enjoy your PCIe tutorial series. It is a good supplement to the PCIe book from Mindshare. I’d like to learn some details about retry, flow control, low power, link training, etc. Do you plan to cover…[Read more]
Universal Verification Methodology (UVM)-Based Stream Generator Environment for RISC-V Cores
Contributed by Google, the environment provides configurable, highly stressful instruction sequences that can verify architectural and micro-architectural corner-cases of designs.
What hollis mentioned is on the RTL side.In fact test cases tend to have their own test tasks, sequences, etc. The compiled library will be different even RTL is the same. So in regression tests, each test has their compiled library. Yes it is not optimal due to long compilation time. One…[Read more]
MS powerpoint doesn’t have built-in electronics symbols. But if you google “electronics symbol for PPT”, you will some online resources for it. For example, the following two ppts have good electronics symbols which makes your drawing in PPT much…[Read more]
Good question. Believe it or not, even in large companies, sometimes this issue pops up and not all engineers have a good handling of it. Yes, there is a better way to handle it. You should remove the delta delay due to gating logic. In this way, no matter how many layers of clock gating…[Read more]