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Antara Sarkar
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Which is DFT/BE Friendly Design for Independently Gated Divided Clocks
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Sarkar 04/10/2020 -
Asynchronorous Reset in DFT
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Sarkar 05/21/2019 -
DFT for Low Power Design with Multiple Power Domains
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Sarkar 03/19/2019 -
Consideration of Clock and Reset Handling in DFT
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Sarkar 04/16/2020 5 5/5 (2 ) -
DFT Logic Power Domain and Related Issues in Multiple Power Domain DFT
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Sarkar 04/20/2019 4 4/5 (1 )
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VLSI-expert, a good tutorial blog site about VLSI backend process
Sarkar 06/26/2016 5 5/5 (1 )
Sarkar posted in
ASIC and FPGA 12 months ago · , 0, 0
A #BIST scheme for faster in-system test of automotive ICs
Get this info from Mentor. Interesting content.
Automotive ICs have have strict requirements for in-field and in-system test, including a short test window for key-on, key-off and functional operation. To help designers meet…[Read more]
Sarkar posted in
ASIC and FPGA 1 year, 10 months ago · , 0, 0
Use #lbist and #mbist for in field test
Lbist and mbist are commonly used for chip manufacturing test. But they can be and is being used in infield test.
There are defects which may appear during the field operation of device. The infield failures are mainly because of latent faults which…[Read more]
Sarkar posted in
ASIC and FPGA 2 years, 9 months ago · , 0, 1
#dft difference of #Synchronous #reset and async reset
Sync abd async reset have their pros and cons. Rtl point of view, one signal can be connected to both async reset and sync reset. This is not true for dft. You will see async reset has one extra dft mux on the sync reset to add in dft…[Read more]
Sarkar posted in
Research and Design 2 years, 11 months ago · , 0, 0
#Risc-V, 3D-NAND #flash, #tensor processor, made to to the top 8 innovations in 2017
https://www.eetimes.com/document.asp?doc_id=1332783&page_number=4