Max path delay was used to be sum of max delays of all gates on the path. In deep submicron this is too pessimistic and ends up over constrain the path. Instead delay can be modeled taking into consideration that all cells wont take worst delay simultaneously.…[Read more]
One of its example stitches two scan chains of different clock domains together. I heard it complicated timing closure. How so? At speed is done at each chain separately. Shift clock is slow…[Read more]
Thinking maybe most cases are ok. First all ffs get reset. Then when async reset is deasserted, it doesnt meet timing. But ff outpout is not x if reset value and d pin in are the same. Even not the same, two cycles later it settles down. So out of reset, module does not start immediately,…[Read more]
It is not about the core itself but also the software running on top of it. There are many free ARM code and many ARM experienced programmers out there. That is hard to turn. In addition, I am not sure if ARM changes much. If so, we should see other players quick form alliances to come up…[Read more]
Thanks for bringing up Allan’s blog. Agree. Actually lots of items I have met myself like bad/missing timing constraints, cross-clock domain (aka async logic) as I mentioned above. Backend DFT logic insertion is another big reason for GLS since these logics are not in RTL.