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Quinn Yang
11.0
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OWE (Overall Wafer Effectiveness) and MFU (Mask Field Utilization)
QYang 03/17/2020 -
Digital IC Backend Lab showing the whole BE Process
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QYang 03/07/2016 -
PTPX Peak Power
QYang 01/02/2018 4 4/5 (1 )
QYang posted in
ASIC and FPGA 3 years, 1 month ago · , 1, 1
Lef, lib, and verilog stub files delivered to backend team from hard macro design team
When a hard macro team designs a hard IP such as serdes, pll, eventually they will deliver full GDS to chip backend team. During design phase, they also need to deliver LEF, lib, vstub files to BE. LEF…[Read more]
QYang posted an update 4 years, 5 months ago · , 0, 1
Snug 2014 tutorial slides, Low DPPM and low cost testing for all process nodes and FinFETs (Part III)
See part I for details.
QYang posted an update 4 years, 5 months ago · , 0, 1
Snug 2014 tutorial slides, Low DPPM and low cost testing for all process nodes and FinFETs (Part II)
See part I for details.…[Read more]
QYang posted in
ASIC and FPGA 4 years, 5 months ago · , 5, 4
Snug 2014 tutorial slides, Low DPPM and low cost testing for all process nodes and FinFETs (Part I)
Read this 94-page tutorial from Mark Lin, a Synopsys FAE, today. Recommend for DFT beginners to understand DFT basics and Synopsys DFTMax Ultra.
Most figures below are about scan compress…[Read more]